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Fix compilation with latest Rust #12

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12 changes: 8 additions & 4 deletions src/port.rs
Original file line number Diff line number Diff line change
Expand Up @@ -46,12 +46,14 @@ impl Port {
}

pub unsafe fn set_pin_mode(&mut self, p: usize, mut mode: u32) {
let mut pcr = core::ptr::read_volatile(&self.pcr[p]);
let pcr_ptr = core::ptr::addr_of_mut!(self.pcr[p]);
let mut pcr : u32 = pcr_ptr.read_volatile();
pcr &= 0xFFFFF8FF;
mode &= 0x00000007;
mode <<= 8;
pcr |= mode;
core::ptr::write_volatile(&mut self.pcr[p], pcr);
pcr_ptr.write_volatile(pcr);

}

pub fn name(&self) -> PortName {
Expand Down Expand Up @@ -84,13 +86,15 @@ impl Gpio {

pub fn output(&mut self) {
unsafe {
core::ptr::write_volatile(&mut (*self.gpio).pddr[self.pin], 1);
let pddr_ptr = core::ptr::addr_of_mut!((*self.gpio).pddr[self.pin]);
pddr_ptr.write_volatile(1);
}
}

pub fn high(&mut self) {
unsafe {
core::ptr::write_volatile(&mut (*self.gpio).psor[self.pin], 1);
let psor_ptr = core::ptr::addr_of_mut!((*self.gpio).psor[self.pin]);
psor_ptr.write_volatile(1);
}
}
}
5 changes: 3 additions & 2 deletions src/sim.rs
Original file line number Diff line number Diff line change
Expand Up @@ -42,9 +42,10 @@ impl Sim {
unsafe {
match clock {
Clock::PortC => {
let mut scgc = core::ptr::read_volatile(&self.scgc5);
let scgc_ptr = core::ptr::addr_of_mut!(self.scgc5);
let mut scgc = scgc_ptr.read_volatile();
scgc |= 0x00000800;
core::ptr::write_volatile(&mut self.scgc5, scgc);
scgc_ptr.write_volatile(scgc);
}
}
}
Expand Down
17 changes: 10 additions & 7 deletions src/watchdog.rs
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
use core;
use core::arch::arm::__NOP;
use core::arch::arm::__nop;

#[repr(C,packed)]
pub struct Watchdog {
Expand All @@ -24,13 +24,16 @@ impl Watchdog {

pub fn disable(&mut self) {
unsafe {
core::ptr::write_volatile(&mut self.unlock, 0xC520);
core::ptr::write_volatile(&mut self.unlock, 0xD928);
__NOP();
__NOP();
let mut ctrl = core::ptr::read_volatile(&self.stctrlh);
let unlock_ptr = core::ptr::addr_of_mut!(self.unlock);
unlock_ptr.write_volatile(0xC520);
unlock_ptr.write_volatile(0xD928);
__nop();
__nop();
let ctrl_ptr = core::ptr::addr_of_mut!(self.stctrlh);
let mut ctrl = ctrl_ptr.read_volatile();
ctrl &= !(0x00000001);
core::ptr::write_volatile(&mut self.stctrlh, ctrl);
ctrl_ptr.write_volatile(ctrl);

}
}
}