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AArch64 update to LLVM 18 #2298
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Commits on Jul 4, 2024
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Change MCPhysReg type to int16_t as LLVM 18 dictates.
With LLVM 18 the MCPhysReg value's type is changed to int16_t. If we update modules to LLVM 18, they will generate compiler warnings that uint16_t* should not be casted to int16_t*. This makes changing the all tables to int16_t necessary, because the alternative is to duplicate all MCPhysReg related code. Which is even worse.
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Don't warn about padding issues.
They break automatically initialized structs we can not change easily.
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The enum values were different and hence lead to different decoding.
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- Splits SME operands in Matrix and Predicate operands. - Fixes general problems of incorrect detections with the vector select/index operands of predicate registers. - Simplifies code.
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Fix special case of SVE2 operands.
Apparently ZT0 registers can an index attached, get which is BOUND to it. We have no "index for reg" field. So it is simply saved as an immediate.
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