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AArch64 update to LLVM 18 #2298

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9958346
Run clang-format
Rot127 Mar 25, 2024
b0e3903
Remove arm.h header from AArch64 files
Rot127 Mar 25, 2024
18e9077
Update all AArch64 module files to LLVM-18.
Rot127 Apr 25, 2024
78986c9
Add check if the differs save file is up-to-date with the current files.
Rot127 Apr 25, 2024
cfddcc3
Add new generator for MC test trnaslation.
Rot127 Apr 26, 2024
b09ec4d
Fix warnings
Rot127 Apr 30, 2024
9aa6934
Update generated AsmWriter files
Rot127 Apr 30, 2024
ad19cb4
Remove unused variable
Rot127 Apr 30, 2024
73384d6
Change MCPhysReg type to int16_t as LLVM 18 dictates.
Rot127 Apr 30, 2024
34ece80
Assign enum values to raw_struct member
Rot127 Apr 30, 2024
b13fd7e
Add printAdrAdrpLabel def
Rot127 Apr 30, 2024
f02436f
Add header to regression test files.
Rot127 May 10, 2024
87fc295
Write files to build dir and ignore more parsing errors.
Rot127 May 10, 2024
ce66e81
Fix parsing of MC test files.
Rot127 May 10, 2024
9101e35
Reset parser after every block
Rot127 May 10, 2024
603b417
Add write and patch header step.
Rot127 May 10, 2024
e667df4
Add and update MC tests for AArch64
Rot127 May 11, 2024
6dd9492
Fix clang-tidy warnings
Rot127 May 11, 2024
886359a
Don't warn about padding issues.
Rot127 May 11, 2024
126d2ed
Fix: Incorrect access of LLVM instruction descriptions.
Rot127 May 15, 2024
227144c
Initialize DecoderComplete flag
Rot127 May 15, 2024
8b3109a
Add more mapping and flag details
Rot127 May 15, 2024
13b90ed
Add function to get MCInstDesc from table
Rot127 May 15, 2024
1d6495b
Fix incorrect memory operand access types.
Rot127 May 15, 2024
cd4d42a
Fix test where memory was not written, ut only read.
Rot127 May 15, 2024
66d9149
Attempt to fix Windows build
Rot127 May 15, 2024
82e050e
Fix 2268
Rot127 May 16, 2024
d3399bb
Refactor SME operands.
Rot127 May 20, 2024
d73ad6d
Fix up typo in WRITE
Rot127 May 21, 2024
5946e68
Print actual path to struct fields
Rot127 May 21, 2024
2b09417
Add Registers of SME operands to the reg-read list
Rot127 May 21, 2024
306decd
Add tests for SME operands.
Rot127 May 21, 2024
5d4010f
Use Capstone reg enum for comparison
Rot127 May 21, 2024
fd3e945
Fix tests: 'Vector arra...' to 'operands[x].vas'
Rot127 May 21, 2024
f754b1e
Add the developer fuzz option.
Rot127 May 21, 2024
d3e83f2
Fix Python bindings for SME operands
Rot127 May 21, 2024
e565056
Fix variable shadowing.
Rot127 May 21, 2024
e9bd84f
Fix clang-tidy warnings
Rot127 May 21, 2024
8e58085
Add missing break.
Rot127 May 21, 2024
116cd12
Fix varg usage
Rot127 May 21, 2024
8fd8314
Allow None as valid value in MC tests.
Rot127 May 21, 2024
146b0a0
Brackets for case
Rot127 May 21, 2024
ab2be32
Handle AArch64_OP_GROUP_AdrAdrpLabel
Rot127 May 21, 2024
7817b14
Fix endian issue with fuzzing start bytes
Rot127 May 21, 2024
52417e1
Move previous sme.pred to it's own operand type.
Rot127 May 22, 2024
211457d
Fix calculation for imm ranges
Rot127 May 22, 2024
c57611f
Print list member flag
Rot127 May 22, 2024
bc0fc06
Fix up operand strings for cstest
Rot127 May 22, 2024
1122863
Do only a shallow clone of the cmocka stable branch
Rot127 May 22, 2024
1371563
Fix: Don't categorize ZT0 as a SME matrix operand.
Rot127 May 26, 2024
8d2f81d
Remove unused code.
Rot127 May 26, 2024
2306d05
Add flag to distinguish Vn and Qn registers.
Rot127 May 26, 2024
98962e5
Add all registers to detail struct, even if emitted in the asm text
Rot127 May 28, 2024
f771694
Fix: Increment op count after each list member is added.
Rot127 May 28, 2024
c98c73d
Remove implicit write to NZCV for MSR Imm instructions.
Rot127 May 28, 2024
2579e49
Handle several alias operands.
Rot127 May 28, 2024
057085b
Add details for zero alias with za0.h
Rot127 May 29, 2024
589293b
Add SME tile to write list if written
Rot127 May 29, 2024
3dbed4a
Add write access flags to operands which are zeroed.
Rot127 May 29, 2024
422fd45
Add SME tests of #2285
Rot127 May 29, 2024
8124a56
Fix tests with latest syntax changes.
Rot127 May 29, 2024
1302062
Fix segfault if memory operand is only a label without register.
Rot127 May 29, 2024
e39c3eb
Fix python bindings
Rot127 Jun 4, 2024
57b2e15
Alually skip a test case if it wasn't parsed.
Rot127 Jun 4, 2024
e32db6a
Attempt to fix clang-tidy warning for some configurations.
Rot127 Jun 6, 2024
f97af0e
Add missing test file (accidentially blocked by gitignore.)
Rot127 Jun 6, 2024
e038aa6
Print clang-tidy version before linting.
Rot127 Jun 6, 2024
60de2e9
Update differ save file
Rot127 Jun 6, 2024
6857d07
Formatting
Rot127 Jun 6, 2024
743f45a
Use clang-tidy-15 as if possible.
Rot127 Jun 6, 2024
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5 changes: 5 additions & 0 deletions .github/workflows/auto-sync.yml
Original file line number Diff line number Diff line change
Expand Up @@ -64,3 +64,8 @@ jobs:
- name: Test Header patcher
run: |
python -m unittest src/autosync/Tests/test_header_patcher.py
python -m unittest src/autosync/Tests/test_mcupdater.py

- name: Differ - Test save file is up-to-date
run: |
./src/autosync/cpptranslator/Differ.py -a AArch64 --check_saved
4 changes: 4 additions & 0 deletions .github/workflows/clang-tidy.yml
Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,10 @@ jobs:
CC=clang sudo cmake --build . --config Release
cd ..

- name: Install clang-tidy-15
run: |
sudo apt install clang-tidy-15

- name: Check for warnings
env:
base_sha: ${{ github.event.pull_request.base.sha }}
Expand Down
1 change: 1 addition & 0 deletions CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -867,6 +867,7 @@ if(CAPSTONE_BUILD_CSTEST)
PREFIX extern
GIT_REPOSITORY "https://git.cryptomilk.org/projects/cmocka.git"
GIT_TAG "origin/stable-1.1"
GIT_SHALLOW true
CONFIGURE_COMMAND cmake -DBUILD_SHARED_LIBS=OFF ../cmocka_ext/
BUILD_COMMAND cmake --build . --config Release
INSTALL_COMMAND ""
Expand Down
26 changes: 18 additions & 8 deletions MCInst.c
Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */

#if defined(CAPSTONE_HAS_OSXKERNEL)
#include <Availability.h>
#include <libkern/libkern.h>
Expand All @@ -11,6 +10,7 @@
#include <string.h>
#include <assert.h>

#include "MCInstrDesc.h"
#include "MCInst.h"
#include "utils.h"

Expand Down Expand Up @@ -224,16 +224,26 @@ bool MCInst_isPredicable(const MCInstrDesc *MIDesc)
/// Checks if tied operands exist in the instruction and sets
/// - The writeback flag in detail
/// - Saves the indices of the tied destination operands.
void MCInst_handleWriteback(MCInst *MI, const MCInstrDesc *InstDesc)
{
const MCOperandInfo *OpInfo = InstDesc[MCInst_getOpcode(MI)].OpInfo;
unsigned short NumOps = InstDesc[MCInst_getOpcode(MI)].NumOperands;
void MCInst_handleWriteback(MCInst *MI, const MCInstrDesc *InstDescTable, unsigned tbl_size)
{
const MCInstrDesc *InstDesc = NULL;
const MCOperandInfo *OpInfo = NULL;
unsigned short NumOps = 0;
if (MI->csh->arch == CS_ARCH_ARM) {
// Uses old (pre LLVM 18) indexing method.
InstDesc = &InstDescTable[MCInst_getOpcode(MI)];
OpInfo = InstDescTable[MCInst_getOpcode(MI)].OpInfo;
NumOps = InstDescTable[MCInst_getOpcode(MI)].NumOperands;
} else {
InstDesc = MCInstrDesc_get(MCInst_getOpcode(MI), InstDescTable, tbl_size);
OpInfo = MCInstrDesc_get(MCInst_getOpcode(MI), InstDescTable, tbl_size)->OpInfo;
NumOps = MCInstrDesc_get(MCInst_getOpcode(MI), InstDescTable, tbl_size)->NumOperands;
}

unsigned i;
for (i = 0; i < NumOps; ++i) {
for (unsigned i = 0; i < NumOps; ++i) {
if (MCOperandInfo_isTiedToOp(&OpInfo[i])) {
int idx = MCOperandInfo_getOperandConstraint(
&InstDesc[MCInst_getOpcode(MI)], i,
InstDesc, i,
MCOI_TIED_TO);

if (idx == -1)
Expand Down
2 changes: 1 addition & 1 deletion MCInst.h
Original file line number Diff line number Diff line change
Expand Up @@ -158,7 +158,7 @@ void MCInst_addOperand2(MCInst *inst, MCOperand *Op);

bool MCInst_isPredicable(const MCInstrDesc *MIDesc);

void MCInst_handleWriteback(MCInst *MI, const MCInstrDesc *InstDesc);
void MCInst_handleWriteback(MCInst *MI, const MCInstrDesc *InstDescTable, unsigned tbl_size);

bool MCInst_opIsTied(const MCInst *MI, unsigned OpNum);

Expand Down
9 changes: 8 additions & 1 deletion MCInstrDesc.c
Original file line number Diff line number Diff line change
Expand Up @@ -38,4 +38,11 @@ int MCOperandInfo_getOperandConstraint(const MCInstrDesc *InstrDesc,
return (OpInfo.Constraints >> ValuePos) & 0xf;
}
return -1;
}
}

/// Returns the instruction description for the given MCInst opcode.
/// Function should be called like:
/// MCInstrDesc_get(MCInst_getOpcode(MI), ARCHInstDesc, ARR_SIZE(ARCHInstDesc));
const MCInstrDesc *MCInstrDesc_get(unsigned opcode, const MCInstrDesc *table, unsigned tbl_size) {
return &table[tbl_size - 1 - opcode];
}
4 changes: 4 additions & 0 deletions MCInstrDesc.h
Original file line number Diff line number Diff line change
Expand Up @@ -163,5 +163,9 @@ bool MCOperandInfo_isTiedToOp(const MCOperandInfo *m);
int MCOperandInfo_getOperandConstraint(const MCInstrDesc *OpInfo,
unsigned OpNum,
MCOI_OperandConstraint Constraint);
const MCInstrDesc *MCInstrDesc_get(unsigned opcode,
const MCInstrDesc *table,
unsigned tbl_size);


#endif
2 changes: 1 addition & 1 deletion MCRegisterInfo.h
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@

/// An unsigned integer type large enough to represent all physical registers,
/// but not necessarily virtual registers.
typedef uint16_t MCPhysReg;
typedef int16_t MCPhysReg;
typedef const MCPhysReg* iterator;

typedef struct MCRegisterClass2 {
Expand Down
1 change: 1 addition & 0 deletions Mapping.h
Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,7 @@ typedef struct insn_map {
bool indirect_branch; // indirect branch instruction?
union {
ppc_suppl_info ppc;
aarch64_suppl_info aarch64;
} suppl_info; // Supplementary information for each instruction.
#endif
} insn_map;
Expand Down