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ci: migrate windows to github workflow #158

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Apr 21, 2024
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ on:
- push
- pull_request

name: stable-only
name: extra-checks

jobs:
test:
Expand Down
8 changes: 5 additions & 3 deletions .github/workflows/main.yml
Original file line number Diff line number Diff line change
Expand Up @@ -6,17 +6,19 @@ name: main

jobs:
test:
runs-on: ubuntu-latest
strategy:
fail-fast: false
matrix:
rust:
# Don't pull in newest dependencies when using old Rust toolchain
- version: 1.70.0
- version: 1.70.0 # MSRV
env: SKIP_CARGO_UPDATE=1
- version: stable
- version: beta
- version: nightly
os:
- ubuntu-latest
- windows-latest
runs-on: ${{ matrix.os }}

steps:
- uses: actions/checkout@v2
Expand Down
37 changes: 0 additions & 37 deletions appveyor.yml

This file was deleted.

21 changes: 17 additions & 4 deletions capstone-rs/ci/test.sh
Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,7 @@ export RUST_BACKTRACE=1
SHOULD_FAIL=${SHOULD_FAIL:-} # Default to false
VALGRIND_TESTS=${VALGRIND_TESTS:-}
CARGO="${CARGO:-cargo}"
UNAME="$(uname)"

# Feature vars
if [ -n "${ALL_FEATURES:-}" ] && [ -n "${NO_DEFAULT_FEATURES:-}" ]; then
Expand Down Expand Up @@ -66,13 +67,21 @@ echo "Running as USER=$USER"
echo "Test should $EXPECTED_RESULT"

if ! [ "${OS_NAME:-}" ]; then
case "$(uname)" in
case "${UNAME}" in
CYGWIN*|MINGW*|MSYS_NT*) OS_NAME=windows ;;
Linux) OS_NAME=linux ;;
Darwin) OS_NAME=osx ;;
FreeBSD) OS_NAME=freebsd ;;
esac
fi

true_path() {
case "${OS_NAME}" in
windows) cygpath -m "$@" ;;
*) echo "$@" ;;
esac
}

# Usage: SHOULD_FAIL [ARG1 [ARG2 [...]]]
expect_exit_status() {
local SHOULD_FAIL="$1"
Expand Down Expand Up @@ -216,7 +225,7 @@ test_rust_file() {
tmp_dir="$(mktemp -d /tmp/rust.testdir.XXXXXXXXXX)"
[ -d "$tmp_dir" ] || Error "Could not make temp dir"

capstone_dir="$(pwd)"
capstone_dir="$(true_path "$(pwd)")"
cd "$tmp_dir"
${CARGO} new --bin test_project -v
cd test_project
Expand Down Expand Up @@ -293,8 +302,12 @@ run_tests() {

cargo_update() {
if [ -z "${SKIP_CARGO_UPDATE:-}" ]; then
echo "Updating dependencies in Cargo.lock"
${CARGO} update
if [[ -n "${CI:-}" ]]; then
echo "Updating dependencies in Cargo.lock"
${CARGO} update
else
echo "Skipping 'cargo update' since we are not in CI"
fi
else
echo "Skipping 'cargo update' since SKIP_CARGO_UPDATE is set"
fi
Expand Down
4 changes: 2 additions & 2 deletions capstone-rs/src/arch/arm64.rs
Original file line number Diff line number Diff line change
Expand Up @@ -300,7 +300,7 @@ mod test {
Imm(42),
);
t(
(ARM64_OP_REG_MRS, cs_arm64_op__bindgen_ty_2 { reg: ARM64_SYSREG_MDRAR_EL1 as u32 }),
(ARM64_OP_REG_MRS, cs_arm64_op__bindgen_ty_2 { reg: ARM64_SYSREG_MDRAR_EL1 as arm64_reg::Type }),
RegMrs(ARM64_SYSREG_MDRAR_EL1),
);
t(
Expand All @@ -317,7 +317,7 @@ mod test {
);
t(
(ARM64_OP_REG_MSR, cs_arm64_op__bindgen_ty_2 {
reg: arm64_sysreg::ARM64_SYSREG_ICC_EOIR1_EL1 as u32 }),
reg: arm64_sysreg::ARM64_SYSREG_ICC_EOIR1_EL1 as arm64_reg::Type }),
RegMsr(arm64_sysreg::ARM64_SYSREG_ICC_EOIR1_EL1),
);
t(
Expand Down
8 changes: 1 addition & 7 deletions capstone-rs/src/instruction.rs
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
use alloc::{self, boxed::Box};
use core::convert::{TryFrom, TryInto};
use core::convert::TryFrom;
use core::fmt::{self, Debug, Display, Error, Formatter};
use core::marker::PhantomData;
use core::ops::Deref;
Expand Down Expand Up @@ -64,12 +64,6 @@ impl RegId {
pub const INVALID_REG: Self = Self(0);
}

impl core::convert::From<u32> for RegId {
fn from(v: u32) -> RegId {
RegId(v.try_into().ok().unwrap_or(Self::INVALID_REG.0))
}
}

/// Represents how the register is accessed.
#[derive(Copy, Clone, Debug, Hash, PartialEq, Eq)]
pub enum RegAccessType {
Expand Down
79 changes: 43 additions & 36 deletions capstone-rs/src/test.rs
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,8 @@
clippy::upper_case_acronyms
)]

use core::{convert::TryInto, fmt::Debug};

use alloc::vec::Vec;
#[cfg(feature = "full")]
use {alloc::string::String, std::collections::HashSet};
Expand Down Expand Up @@ -288,7 +290,7 @@ fn test_instruction_detail_helper<T>(
#[cfg(feature = "full")]
/// Assert instruction belongs or does not belong to groups, testing both insn_belongs_to_group
/// and insn_group_ids
fn test_instruction_group_helper<R: Copy + Into<RegId>>(
fn test_instruction_group_helper<R: Copy + Debug + TryInto<RegIdInt>>(
cs: &Capstone,
insn: &Insn,
mnemonic_name: &str,
Expand Down Expand Up @@ -328,7 +330,15 @@ fn test_instruction_group_helper<R: Copy + Into<RegId>>(

macro_rules! assert_regs_match {
($expected:expr, $actual_regs:expr, $msg:expr) => {{
let mut expected_regs: Vec<RegId> = $expected.iter().map(|&x| x.into()).collect();
let mut expected_regs: Vec<RegId> = $expected
.iter()
.map(|&x| {
RegId(
x.try_into()
.unwrap_or_else(|_| panic!("Failed to convert {:?} to RegIdInt", x)),
)
})
.collect();
expected_regs.sort_unstable();
let mut regs: Vec<RegId> = $actual_regs.iter().map(|&x| x.into()).collect();
regs.sort_unstable();
Expand Down Expand Up @@ -357,7 +367,7 @@ type ExpectedInsns<'a, R> = (
);

#[allow(unused)]
fn instructions_match_group<R: Copy + Into<RegId>>(
fn instructions_match_group<R: Copy + Debug + TryInto<RegIdInt>>(
cs: &mut Capstone,
expected_insns: &[ExpectedInsns<R>],
has_default_syntax: bool,
Expand Down Expand Up @@ -2483,13 +2493,10 @@ fn test_arch_systemz() {

#[test]
fn test_arch_tms320c64x_detail() {
use crate::arch::tms320c64x::Tms320c64xOperand::*;
use crate::arch::tms320c64x::Tms320c64xReg::*;
use crate::arch::tms320c64x::*;
use capstone_sys::tms320c64x_funit::*;
use capstone_sys::tms320c64x_mem_dir::*;
use capstone_sys::tms320c64x_mem_disp::*;
use capstone_sys::tms320c64x_mem_mod::*;
use crate::arch::tms320c64x::{
Tms320c64xFuntionalUnit, Tms320c64xMemDirection, Tms320c64xMemDisplayType,
Tms320c64xMemModify, Tms320c64xOpMem, Tms320c64xOperand::*, Tms320c64xReg::*,
};
use capstone_sys::tms320c64x_op_mem;

test_arch_mode_endian_insns_detail(
Expand Down Expand Up @@ -2529,13 +2536,13 @@ fn test_arch_tms320c64x_detail() {
b"\x02\x80\x46\x9e",
&[
Mem(Tms320c64xOpMem(tms320c64x_op_mem {
base: TMS320C64X_REG_B15,
base: TMS320C64X_REG_B15 as c_uint,
disp: 0x46,
unit: TMS320C64X_FUNIT_L as c_uint,
unit: Tms320c64xFuntionalUnit::L as c_uint,
scaled: false as c_uint,
disptype: TMS320C64X_MEM_DISP_CONSTANT as c_uint,
direction: TMS320C64X_MEM_DIR_FW as c_uint,
modify: TMS320C64X_MEM_MOD_NO as c_uint,
disptype: Tms320c64xMemDisplayType::Constant as c_uint,
direction: Tms320c64xMemDirection::Forward as c_uint,
modify: Tms320c64xMemModify::No as c_uint,
})),
Reg(RegId(TMS320C64X_REG_B5 as RegIdInt)),
],
Expand All @@ -2548,13 +2555,13 @@ fn test_arch_tms320c64x_detail() {
b"\x02\x90\x32\x96",
&[
Mem(Tms320c64xOpMem(tms320c64x_op_mem {
base: TMS320C64X_REG_A4,
base: TMS320C64X_REG_A4 as c_uint,
disp: 0x1,
unit: TMS320C64X_FUNIT_L as c_uint,
unit: Tms320c64xFuntionalUnit::L as c_uint,
scaled: true as c_uint,
disptype: TMS320C64X_MEM_DISP_CONSTANT as c_uint,
direction: TMS320C64X_MEM_DIR_FW as c_uint,
modify: TMS320C64X_MEM_MOD_PRE as c_uint,
disptype: Tms320c64xMemDisplayType::Constant as c_uint,
direction: Tms320c64xMemDirection::Forward as c_uint,
modify: Tms320c64xMemModify::Pre as c_uint,
})),
Reg(RegId(TMS320C64X_REG_B5 as RegIdInt)),
],
Expand All @@ -2565,13 +2572,13 @@ fn test_arch_tms320c64x_detail() {
b"\x02\x80\x46\x9e",
&[
Mem(Tms320c64xOpMem(tms320c64x_op_mem {
base: TMS320C64X_REG_B15,
base: TMS320C64X_REG_B15 as c_uint,
disp: 0x46,
unit: TMS320C64X_FUNIT_L as c_uint,
unit: Tms320c64xFuntionalUnit::L as c_uint,
scaled: false as c_uint,
disptype: TMS320C64X_MEM_DISP_CONSTANT as c_uint,
direction: TMS320C64X_MEM_DIR_FW as c_uint,
modify: TMS320C64X_MEM_MOD_NO as c_uint,
disptype: Tms320c64xMemDisplayType::Constant as c_uint,
direction: Tms320c64xMemDirection::Forward as c_uint,
modify: Tms320c64xMemModify::No as c_uint,
})),
Reg(RegId(TMS320C64X_REG_B5 as RegIdInt)),
],
Expand All @@ -2582,13 +2589,13 @@ fn test_arch_tms320c64x_detail() {
b"\x05\x3c\x83\xe6",
&[
Mem(Tms320c64xOpMem(tms320c64x_op_mem {
base: TMS320C64X_REG_A15,
base: TMS320C64X_REG_A15 as c_uint,
disp: 0x4,
unit: TMS320C64X_FUNIT_L as c_uint,
unit: Tms320c64xFuntionalUnit::L as c_uint,
scaled: true as c_uint,
disptype: TMS320C64X_MEM_DISP_CONSTANT as c_uint,
direction: TMS320C64X_MEM_DIR_FW as c_uint,
modify: TMS320C64X_MEM_MOD_NO as c_uint,
disptype: Tms320c64xMemDisplayType::Constant as c_uint,
direction: Tms320c64xMemDirection::Forward as c_uint,
modify: Tms320c64xMemModify::No as c_uint,
})),
RegPair(
RegId(TMS320C64X_REG_B11 as RegIdInt),
Expand All @@ -2602,13 +2609,13 @@ fn test_arch_tms320c64x_detail() {
b"\x0b\x0c\x8b\x24",
&[
Mem(Tms320c64xOpMem(tms320c64x_op_mem {
base: TMS320C64X_REG_A3,
base: TMS320C64X_REG_A3 as c_uint,
disp: TMS320C64X_REG_A4 as c_uint,
unit: TMS320C64X_FUNIT_D as c_uint,
unit: Tms320c64xFuntionalUnit::D as c_uint,
scaled: false as c_uint,
disptype: TMS320C64X_MEM_DISP_REGISTER as c_uint,
direction: TMS320C64X_MEM_DIR_FW as c_uint,
modify: TMS320C64X_MEM_MOD_NO as c_uint,
disptype: Tms320c64xMemDisplayType::Register as c_uint,
direction: Tms320c64xMemDirection::Forward as c_uint,
modify: Tms320c64xMemModify::No as c_uint,
})),
RegPair(
RegId(TMS320C64X_REG_A23 as RegIdInt),
Expand Down Expand Up @@ -3147,7 +3154,7 @@ fn test_arch_riscv_detail() {
&[
Reg(RegId(RISCV_REG_X4 as RegIdInt)),
Mem(RiscVOpMem(riscv_op_mem {
base: RISCV_REG_X5,
base: RISCV_REG_X5 as c_uint,
disp: 8,
})),
],
Expand Down