Merge pull request #116 from casper-astro/casper-astro-soak-test

Casper astro soak test

casper_library/adder_tree_init.m

@@ -41,6 +41,7 @@ function adder_tree_init(blk,varargin)
     'csp_latency', 1, ....
     'first_stage_hdl', 'off', ...
     'adder_imp', 'Fabric', ...
+    'dvalid_en','off',...
     'floating_point', 'off', ...
     'float_type', 'single', ...
     'exp_width', 8, ...
@@ -55,6 +56,7 @@ function adder_tree_init(blk,varargin)
   latency           = get_var('csp_latency', 'defaults', defaults, varargin{:});
   first_stage_hdl   = get_var('first_stage_hdl', 'defaults', defaults, varargin{:});
   adder_imp         = get_var('adder_imp', 'defaults', defaults, varargin{:});
+  dvalid_en         = get_var('dvalid_en', 'defaults', defaults, varargin{:});
   floating_point    = get_var('floating_point', 'defaults', defaults, varargin{:});
   float_type        = get_var('float_type', 'defaults', defaults, varargin{:});
   exp_width         = get_var('exp_width', 'defaults', defaults, varargin{:});
@@ -117,10 +119,17 @@ function adder_tree_init(blk,varargin)
 add_line(blk, 'sync/1', 'sync_delay/1');
 add_line(blk, 'sync_delay/1', 'sync_out/1');
 
+% Take care of dvalid
+if dvalid_en == 1
+    reuse_block(blk, 'dv_in', 'built-in/inport', 'Position', [30 10+20 60 25+20], 'Port', '1');   
+end
+
+
 % Take care of adder tree
 for i=1:n_inputs,
     reuse_block(blk, ['din',num2str(i)], 'built-in/inport', 'Position', [30 i*40+20 60 35+40*i]);
 end
+
 reuse_block(blk, 'dout', 'built-in/outport', 'Position', [30+(stages+1)*100 40 60+(stages+1)*100 55]);
 
 if floating_point == 1
@@ -171,6 +180,14 @@ function adder_tree_init(blk,varargin)
                         'bin_pt',num2str(frac_width), ...
                         'Position', [100 200 120 220]);
 
+
+                    if dvalid_en == 1
+                        set_param([blk, ['/', addr]], 'en', 'on');  
+                        add_line(blk, 'dv_in/1', [addr, '/3'], 'autorouting', 'on');       
+                    else
+                        set_param([blk, ['/', addr]], 'en', 'off'); 
+                    end
+
                     if stage == 1,
                         set_param([blk,'/',addr], 'use_behavioral_HDL', first_stage_hdl);
 
@@ -241,8 +258,16 @@ function adder_tree_init(blk,varargin)
                         'use_behavioral_HDL', behavioral, 'hw_selection', hw_selection, ...
                         'pipelined', 'on', 'use_rpm', 'on', ...
                         'Position', [30+stage*100 j*80-40 70+stage*100 j*80+20]);
+
+                    if dvalid_en == 1
+                        set_param([blk, ['/', addr]], 'en', 'on');  
+                        add_line(blk, 'dv_in/1', [addr, '/3'], 'autorouting', 'on');       
+                    else
+                        set_param([blk, ['/', addr]], 'en', 'off'); 
+                    end
+
                     if stage == 1,
-                set_param([blk,'/',addr], 'use_behavioral_HDL', first_stage_hdl);
+                        set_param([blk,'/',addr], 'use_behavioral_HDL', first_stage_hdl);
                         add_line(blk,['din',num2str((j*2-1)),'/1'],[addr,'/1']);
                         add_line(blk,['din',num2str((j*2)),'/1'],[addr,'/2']);
                     else,

casper_library/bus_mult_init.m

@@ -636,6 +636,8 @@ function bus_mult_init(blk, varargin)
             quant = 'Truncate';
           case 1,
             quant = 'Round  (unbiased: +/- Inf)';
+          case 2,
+            quant = 'Round  (unbiased: Even Values)';
         end  
         switch overflow(index),
           case 0,

casper_library/casper_library_bus_initialize.m

@@ -460,7 +460,7 @@ function bus_mult_mask(blk)
 		'MaskSelfModifiable', sprintf('on'), ...
 		'MaskType', sprintf('bus_mult'), ...
 		'MaskDescription', sprintf('Multiply components of two busses'), ...
-		'MaskPromptString', sprintf('a input bit widths|a input binary points |a input type (Unsigned=0, Signed=1)|a input complex|b input bit widths|b input binary points|b input type (Unsigned=0, Signed=1)|b input complex|misc support|floating point|float type|a input vector in bus|b input vector in bus|fraction width|exponent width|output bit widths|output binary points|output type (Unsigned=0, Signed=1)|quantization strategy (Truncate=0, Round  (unbiased: +/- Inf)=1)|overflow strategy (Wrap=0, Saturate=1, Flag as error=2)|multiplier latency|adder latency|convert latency|limit fanout to ?|fanout register latency|multiplier implementation|pipeline complex mult|pipeline latency'), ...
+		'MaskPromptString', sprintf('a input bit widths|a input binary points |a input type (Unsigned=0, Signed=1)|a input complex|b input bit widths|b input binary points|b input type (Unsigned=0, Signed=1)|b input complex|misc support|floating point|float type|a input vector in bus|b input vector in bus|fraction width|exponent width|output bit widths|output binary points|output type (Unsigned=0, Signed=1)|quantization strategy (Truncate=0, Round  (unbiased: +/- Inf)=1, , Round  (unbiased: Even Values)=2)|overflow strategy (Wrap=0, Saturate=1, Flag as error=2)|multiplier latency|adder latency|convert latency|limit fanout to ?|fanout register latency|multiplier implementation|pipeline complex mult|pipeline latency'), ...
 		'MaskStyleString', sprintf('edit,edit,edit,checkbox,edit,edit,edit,checkbox,checkbox,checkbox,radiobutton(single|custom),edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,popup(behavioral HDL|standard core|embedded multiplier core),checkbox,edit'), ...
 		'MaskCallbackString', sprintf('|||||||||onoff = get_param(gcb, ''floating_point'');\nif strcmp(onoff,''on'')\n    enable_fixpt = ''off'';\n    set_param_state(gcb, ''float_type'', ''on'')\n    \n    set_param_state(gcb, ''input_vec_a'', ''on'')\n    set_param_state(gcb, ''input_vec_b'', ''on'')\n    \n    f_type = get_param(gcb, ''float_type'');\n    if strcmp(f_type,''custom'')\n        set_param_state(gcb, ''exp_width'', ''on'')\n        set_param_state(gcb, ''frac_width'', ''on'')\n    else\n        set_param_state(gcb, ''exp_width'', ''off'')\n        set_param_state(gcb, ''frac_width'', ''off'')\n    end\n   \nelse\n    enable_fixpt = ''on'';\n    set_param_state(gcb, ''float_type'', ''off'')\n    set_param_state(gcb, ''exp_width'', ''off'')\n    set_param_state(gcb, ''frac_width'', ''off'')\n    set_param_state(gcb, ''input_vec_a'', ''off'')\n    set_param_state(gcb, ''input_vec_b'', ''off'')\nend\n\nset_param_state(gcb, ''n_bits_a'', enable_fixpt)\nset_param_state(gcb, ''bin_pt_a'', enable_fixpt)\nset_param_state(gcb, ''type_a'', enable_fixpt)\nset_param_state(gcb, ''n_bits_b'', enable_fixpt)\nset_param_state(gcb, ''bin_pt_b'', enable_fixpt)\nset_param_state(gcb, ''type_b'', enable_fixpt)\n\nset_param_state(gcb, ''n_bits_out'', enable_fixpt)\nset_param_state(gcb, ''bin_pt_out'', enable_fixpt)\nset_param_state(gcb, ''type_out'', enable_fixpt)\nset_param_state(gcb, ''quantization'', enable_fixpt)\nset_param_state(gcb, ''overflow'', enable_fixpt)\n\n\n\n\n\n|f_type = get_param(gcb, ''float_type'');\nif strcmp(f_type,''custom'')\n    set_param_state(gcb, ''exp_width'', ''on'')\n    set_param_state(gcb, ''frac_width'', ''on'')\nelse\n    set_param_state(gcb, ''exp_width'', ''off'')\n    set_param_state(gcb, ''frac_width'', ''off'')\nend||||||||||||||||pipeline_en = get_param(gcb, ''pipeline_cmult_en'');\nif strcmp(pipeline_en,''on'')\n\n    set_param_state(gcb, ''pipeline_latency'', ''on'')\nelse\n    set_param_state(gcb, ''pipeline_latency'', ''off'')\nend\n|'), ...
 		'MaskEnableString', sprintf('on,on,on,on,on,on,on,on,on,on,off,off,off,off,off,on,on,on,on,on,on,on,on,on,on,on,on,off'), ...

casper_library/dec_fir_async_init.m

@@ -124,24 +124,43 @@ function dec_fir_async_init(blk)
     sync_latency = add_latency + sync_latency;
 end
 % if delay is greater than 17*3 then might as well use logic as using more than 3 SRL16s and sync_delay uses approx 3 (2 comparators, one counter) 
-if sync_latency > 17*3,
-    sync_delay_block = 'casper_library_delays/sync_delay';
-    parm_name = 'DelayLen';
-else 
-    sync_delay_block = 'xbsIndex_r4/Delay';
-    parm_name = 'latency';
+% if sync_latency > 17*3,
+%     sync_delay_block = 'casper_library_delays/sync_delay';
+%     parm_name = 'DelayLen';
+% else 
+%     sync_delay_block = 'xbsIndex_r4/Delay';
+%     parm_name = 'latency';
+% end
+
+% NOTE: The above code is commented out as we need an enable for the delay
+% block. This may be added to the casper library delay block later
+% New:
+sync_delay_block = 'xbsIndex_r4/Delay';
+parm_name = 'latency';
+
+
+
+
+if async_ops
+   dvalid_en = 'on';    
+else
+   dvalid_en = 'off';
 end
+
 reuse_block(blk, 'sync_in', 'built-in/inport', ...
     'Position', [0 20 30 36], 'Port', '1');
 reuse_block(blk, 'sync_delay', sync_delay_block, ...
     'Position', [60 8 100 48], ...
+    'en', dvalid_en, ...
     parm_name, num2str(sync_latency));
+
 % reuse_block(blk, 'sync_goto', 'built-in/goto', ...
 %         'GotoTag', 'sync_in', 'showname', showname, ...
 %         'Position', [130, 20, 130+sizex_goto, 20+sizey_goto]);
 add_line(blk, 'sync_in/1', 'sync_delay/1');
 % add_line(blk, 'sync_delay/1', 'sync_goto/1');
 
+
 % dv in
 dv_latency = sync_latency + (ceil(log2(num_fir_col))*add_latency);
 data_port_start = 2;
@@ -152,6 +171,11 @@ function dec_fir_async_init(blk)
         ypos = n_inputs*60 + 300;
     end
     data_port_start = 3;
+
+    % Overwrite dv_latency: Empiricaltests showed it was equal to
+    % num_fir_col. THIS NEEDS TO BE VERIFIED!
+    dv_latency = num_fir_col;
+
     reuse_block(blk, 'dv_in', 'built-in/inport', ...
         'Position', [0 ypos 30 ypos+16], 'Port', '2');
     reuse_block(blk, 'dv_delay', 'xbsIndex_r4/Delay', ...
@@ -165,6 +189,13 @@ function dec_fir_async_init(blk)
 %             'GotoTag', 'dv_in', 'showname', showname, ...
 %             'Position', [60, 50, 60+sizex_goto, 50+sizey_goto]);
 %     add_line(blk, 'dv_in/1', 'dv_goto/1');
+
+    add_line(blk, 'dv_in/1', 'sync_delay/2');
+
+    % NEW: Halt sync if the DV drops
+    %set_param([blk, '/dv_delay'], 'en', 'on');
+    %add_line(blk, 'dv_in/1', 'dv_delay/2');
+
 end
 
 % data bus in
@@ -193,13 +224,21 @@ function dec_fir_async_init(blk)
   first_stage_hdl_external = 'off';
 end
 
+if async_ops
+    dvalid_en = 'on';
+else
+    dvalid_en = 'off';
+end
+
 reuse_block(blk, 'real_sum', 'casper_library_misc/adder_tree', ...
     'Position', [200*num_fir_col+400 300 200*num_fir_col+460 num_fir_col*10+350], ...
     'n_inputs',num2str(num_fir_col),'csp_latency',num2str(add_latency), ...
+    'dvalid_en', dvalid_en, ... 
     'adder_imp', adder_imp, 'first_stage_hdl', first_stage_hdl_external);
 reuse_block(blk, 'imag_sum', 'casper_library_misc/adder_tree', ...
     'Position', [200*num_fir_col+400 num_fir_col*10+400 200*num_fir_col+460 num_fir_col*20+450], ...
     'n_inputs',num2str(num_fir_col),'csp_latency',num2str(add_latency), ...
+    'dvalid_en', dvalid_en, ... 
     'adder_imp', adder_imp, 'first_stage_hdl', first_stage_hdl_external);
 
 % the tap columns
@@ -259,12 +298,23 @@ function dec_fir_async_init(blk)
                 add_line(blk, [prev_blk_name, '/', num2str(ctr2*2)],   [blk_name, '/', num2str(ctr2*2)]);
             end
         end
-        if coeff_sym,
-            add_line(blk, [blk_name, '/', num2str(n_inputs*4+1)], ['real_sum/', num2str(ctr+1)]);
-            add_line(blk, [blk_name, '/', num2str(n_inputs*4+2)], ['imag_sum/', num2str(ctr+1)]);
+
+        if async_ops,
+            if coeff_sym,
+                add_line(blk, [blk_name, '/', num2str(n_inputs*4+1)], ['real_sum/', num2str(ctr+2)]);
+                add_line(blk, [blk_name, '/', num2str(n_inputs*4+2)], ['imag_sum/', num2str(ctr+2)]);
+            else
+                add_line(blk, [blk_name, '/', num2str(n_inputs*2+1)], ['real_sum/', num2str(ctr+2)]);
+                add_line(blk, [blk_name, '/', num2str(n_inputs*2+2)], ['imag_sum/', num2str(ctr+2)]);
+            end
         else
-            add_line(blk, [blk_name, '/', num2str(n_inputs*2+1)], ['real_sum/', num2str(ctr+1)]);
-            add_line(blk, [blk_name, '/', num2str(n_inputs*2+2)], ['imag_sum/', num2str(ctr+1)]);
+            if coeff_sym,
+                add_line(blk, [blk_name, '/', num2str(n_inputs*4+1)], ['real_sum/', num2str(ctr+1)]);
+                add_line(blk, [blk_name, '/', num2str(n_inputs*4+2)], ['imag_sum/', num2str(ctr+1)]);
+            else
+                add_line(blk, [blk_name, '/', num2str(n_inputs*2+1)], ['real_sum/', num2str(ctr+1)]);
+                add_line(blk, [blk_name, '/', num2str(n_inputs*2+2)], ['imag_sum/', num2str(ctr+1)]);
+            end
         end
         if async_ops,
             if coeff_sym,
@@ -306,10 +356,20 @@ function dec_fir_async_init(blk)
 add_line(blk, 'convert1/1',     'ri_to_c/1');
 add_line(blk, 'convert2/1',     'ri_to_c/2');
 add_line(blk, 'ri_to_c/1',      'dout/1');
-add_line(blk, 'sync_delay/1',   'real_sum/1');
-add_line(blk, 'sync_delay/1',   'imag_sum/1');
+%add_line(blk, 'sync_delay/1',   'real_sum/2');
+%add_line(blk, 'sync_delay/1',   'imag_sum/2');
 add_line(blk, 'real_sum/1',     'sync_out/1');
 
+if async_ops
+    add_line(blk, 'sync_delay/1',   'real_sum/2');
+    add_line(blk, 'sync_delay/1',   'imag_sum/2');
+    add_line(blk, 'dv_in/1', 'real_sum/1');
+    add_line(blk, 'dv_in/1', 'imag_sum/1');  
+else
+    add_line(blk, 'sync_delay/1',   'real_sum/1');
+    add_line(blk, 'sync_delay/1',   'imag_sum/1');   
+end
+
 % backward links for symmetric coefficients
 if coeff_sym,
     if bus_input,

casper_library/dec_fir_init.m

@@ -198,7 +198,7 @@ function dec_fir_init(blk,varargin)
     'latency', num2str(conv_latency), 'quantization', quantization);
 reuse_block(blk, 'convert2', 'xbsIndex_r4/Convert', ...
     'Position', [200*num_fir_col+560 500 200*num_fir_col+590 515], ...
-    'n_bits', num2str(n_bits), 'bin_pt', num2str(n_bits-1), 'arith_type', 'Signed  (2''s comp)', ...
+    'n_bits', num2str(n_bits), 'bin_pt', num2str(n_bits_bp), 'arith_type', 'Signed  (2''s comp)', ...
     'latency', num2str(conv_latency), 'quantization', quantization);
 
 reuse_block(blk, 'ri_to_c', 'casper_library_misc/ri_to_c', ...

casper_library/delay_bram_init.m

@@ -81,11 +81,41 @@ function delay_bram_init(blk, varargin)
     'use_rpm', use_rpm, 'implementation', implementation, ...
     'Position', [95 64 130 96]);
 
+%   reuse_block(blk, 'ram', 'xbsIndex_r4/Single Port RAM', ...
+%     'depth', num2str(2^bitwidth), 'initVector', '0', ...
+%     'distributed_mem', 'Block RAM', ...
+%     'write_mode', 'Read before write', 'en', async, ...
+%     'optimize', 'Area', 'latency', 'bram_latency', ...
+%     'Position', [150 62 215 178]);
+%   add_line(blk, 'counter/1', 'ram/1');
+%   add_line(blk, 'din/1', 'ram/2');
+% 
+%   if strcmp(async,'on'),
+%     add_line(blk, 'en/1', 'counter/1');
+%     add_line(blk, 'en/1', 'ram/3');
+%     add_line(blk, 'en/1', 'ram/4');
+%   else
+%     add_line(blk, 'constant/1', 'ram/3');
+%   end
+% 
+%   reuse_block(blk, 'dout', 'built-in/outport', 'Port', '1', ...
+%       'Position', [240 113 270 127]);
+%   add_line(blk, 'ram/1', 'dout/1');
+
+  % NOTE: The commented code above is the origional draw script. The code 
+  % below is to implement a fix for the Xilinx SPRAM issue when the 'en' 
+  % is used (seems to be ignored and data lateches regardless). This implements
+  % a Xilinx recommended work-around until the issue is fixed in a later
+  % release. Current issue is with Vivado 2019.1.
+
+  % ------------------------  Start of Fix -------------------------------
+
+  bram_latency_ram_only = 1;
   reuse_block(blk, 'ram', 'xbsIndex_r4/Single Port RAM', ...
     'depth', num2str(2^bitwidth), 'initVector', '0', ...
     'distributed_mem', 'Block RAM', ...
     'write_mode', 'Read before write', 'en', async, ...
-    'optimize', 'Area', 'latency', 'bram_latency', ...
+    'optimize', 'Area', 'latency', num2str(bram_latency_ram_only), ...
     'Position', [150 62 215 178]);
   add_line(blk, 'counter/1', 'ram/1');
   add_line(blk, 'din/1', 'ram/2');
@@ -98,9 +128,65 @@ function delay_bram_init(blk, varargin)
     add_line(blk, 'constant/1', 'ram/3');
   end
 
-  reuse_block(blk, 'dout', 'built-in/outport', 'Port', '1', ...
-      'Position', [240 113 270 127]);
-  add_line(blk, 'ram/1', 'dout/1');
+  bram_latency_delays_only = bram_latency-1;
+
+  pos_shift = 0;
+
+  for d_num = 1:bram_latency_delays_only
+     delay_num = ['d' num2str(d_num)];
+
+     reuse_block(blk, delay_num, 'xbsIndex_r4/Delay', ...
+        'Position', [(255 + pos_shift) 113 (285 + pos_shift) 137], ...
+        'latency', '1', ...
+        'en', async, ...
+        'reg_retiming', 'on');
+
+        if strcmp(async,'on'),
+          add_line(blk, 'en/1', [delay_num '/2']);
+        end   
+        pos_shift = pos_shift + 50;
+  end
+
+  for d_num = 1:bram_latency_delays_only
+    if d_num == 1
+        add_line(blk, 'ram/1', 'd1/1');            
+    else
+        delay_num = ['d' num2str(d_num)];
+        prev_delay_num = ['d' num2str(d_num-1)];
+        add_line(blk, [prev_delay_num '/1'], [delay_num '/1']);   
+    end  
+
+    if d_num == bram_latency_delays_only
+      reuse_block(blk, 'dout', 'built-in/outport', 'Port', '1', ...
+          'Position', [(255 + pos_shift) 113 (285 + pos_shift) 127]);
+      add_line(blk, [delay_num '/1'], 'dout/1');        
+    end
+
+  end
+
+
+
+%   reuse_block(blk, 'd0', 'xbsIndex_r4/Delay', ...
+%     'Position', [325 113 355 137], ...
+%     'latency', '1', ...
+%     'en', async, ...
+%     'reg_retiming', 'on');
+%   add_line(blk, 'ram/1', 'd0/1');
+%   add_line(blk, 'en/1', 'd0/2');
+
+%   reuse_block(blk, 'd1', 'xbsIndex_r4/Delay', ...
+%     'Position', [375 113 405 137], ...
+%     'latency', '1', ...
+%     'en', async, ...
+%     'reg_retiming', 'on');
+%   add_line(blk, 'd0/1', 'd1/1');
+%   add_line(blk, 'en/1', 'd1/2');
+
+
+
+
+
+  % --------------------------  End of Fix -------------------------------
 
   clean_blocks(blk);