Merge pull request #123 from ska-sa/devel

Asymmetric BRAM and Red Pitaya compile Fixes

jasper_library/hdl_sources/axi4_lite/axi4lite_pkg.vhd

@@ -133,4 +133,4 @@ package axi4lite_pkg is
      ((OTHERS => '0'), (OTHERS => '0'), (OTHERS => '0'), '0', '0');
    CONSTANT c_axi4stream_siso_rst : t_axi4stream_siso := 
     (tready => '0');
-end axi4lite_pkg; 
+end axi4lite_pkg; 

jasper_library/hdl_sources/forty_gbe/cont_microblaze/EMB123701U1R1.elf

@@ -1 +1 @@
-EMB123701U1R1-v3.20.36-0-g00f7671-master.elf
+EMB123701U1R1-v3.20.58-0-g8c875c6-master.elf

jasper_library/hdl_sources/sys_block/counter.v

@@ -0,0 +1,55 @@
+//============================================================================//
+//                                                                            //
+//      Parameterize Counter                                                  //
+//                                                                            //
+//      Module name: counter                                                  //
+//      Desc: parameterized counter, counts up/down in any increment          //
+//      Date: Oct 2011                                                        //
+//      Developer: Rurik Primiani & Wesley New                                //
+//      Adapted by: Mathews Chirindo                                          //
+//      Date: Jan 2020                                                        //
+//      Licence: GNU General Public License ver 3                             //
+//      Notes:                                                                //
+//                                                                            //
+//============================================================================//
+
+module counter #(
+      //==============================
+      // Top level block parameters
+      //==============================
+      parameter DATA_WIDTH   = 32,               // number of bits in counters
+      parameter COUNT_FROM   = 0,               // start with this number
+      parameter COUNT_TO     = 2**(DATA_WIDTH), // value to count to in CL case
+      parameter STEP         = 1                // negative or positive, sets direction
+   ) (
+      //===============
+      // Input Ports
+      //===============
+      input user_clk,
+      input en,
+      input user_rst,
+
+      //===============
+      // Output Ports
+      //===============
+      output reg [DATA_WIDTH-1:0] count_out,
+      output we
+   );
+
+   assign we = 1'b1;
+
+// Synchronous logic
+   always @(posedge user_clk) begin
+      // if ACTIVE_LOW_RST is defined then reset on a low
+      // this should be defined on a system-wide basis
+       if (`ifdef ACTIVE_LOW_RST user_rst `else !user_rst `endif) begin
+         if (en == 1) begin
+           count_out <= count_out + STEP;
+         end
+       end 
+       else begin
+         count_out <= COUNT_FROM;
+       end // else: if(rst != 0)
+   end
+endmodule
+

jasper_library/memory.py

@@ -1,5 +1,6 @@
 class Register(object):
-    def __init__(self, name, nbytes=4, offset=0, mode='r', default_val=0, ram=False, ram_size=-1):
+    def __init__(self, name, nbytes=4, offset=0, mode='r',
+                default_val=0, ram=False, ram_size=-1, data_width=32):
         """
         A class to encapsulate a register's parameters. This is used when
         instantiating a device with a large address space, but it is desirable
@@ -48,3 +49,8 @@ def modify_top(self,top):
         self.ram = ram
         #self.ram_size = ram_size
         self.default_val = default_val
+
+        # Addded to make provision for variable-size BRAMs in AXI4-Lite devices
+        # - Placing here for now because toolflow.py:generate_xml_memory_map
+        #   has access to the memory.Register object in the XML generation
+        self.data_width = data_width

jasper_library/platforms/red_pitaya_10.yaml

@@ -120,7 +120,129 @@ pins:
   DAC_IQRESET:
     iostd: LVCMOS33
     loc: N15
-
+  FIXED_IO_ddr_vrp:
+    iostd: SSTL15_T_DCI
+    loc: H5
+  FIXED_IO_ddr_vrn:
+    iostd: SSTL15_T_DCI
+    loc: G5
+  DDR_we_n:
+    iostd: SSTL15
+    loc: M5
+  DDR_RAS_n:
+    iostd: SSTL15
+    loc: P4
+  DDR_ODT:
+    iostd: SSTL15
+    loc: N5
+  DDR_reset_n:
+    iostd: SSTL15
+    loc: B4
+  DDR_DQS_p:
+    iostd: DIFF_SSTL15_T_DCI
+    loc:
+       - C2
+       - G2
+       - R2
+       - W5
+  DDR_DQS_n:
+    iostd: DIFF_SSTL15_T_DCI
+    loc:
+       - B2
+       - F2
+       - T2
+       - W4
+  DDR_DQ:
+    iostd: SSTL15_T_DCI
+    loc:
+       - C3
+       - B3
+       - A2
+       - A4
+       - D3
+       - D1
+       - C1
+       - E1
+       - E2
+       - E3
+       - G3
+       - H3
+       - J3
+       - H2
+       - H1
+       - J1
+       - P1
+       - P3
+       - R3
+       - R1
+       - T4
+       - U4
+       - U2
+       - U3
+       - V1
+       - Y3
+       - W1
+       - Y4
+       - Y2
+       - W3
+       - V2
+       - V3
+  DDR_DM:
+    iostd: DIFF_SSTL15_T_DCI
+    loc:
+       - A1
+       - F1
+       - T1
+       - Y1
+  DDR_CS_n:
+    iostd: SSTL15
+    loc: N1
+  DDR_CKE:
+    iostd: SSTL15
+    loc: N3
+  DDR_Ck_p:
+    iostd: SSTL15
+    loc: L2
+  DDR_Ck_n:
+    iostd: SSTL15
+    loc: M2
+  DDR_CAS_n:
+    iostd: SSTL15
+    loc: P5
+  DDR_ba:
+    iostd: DIFF_SSTL15
+    loc:
+       - L5
+       - R4
+       - J5
+  DDR_Addr:
+    iostd: SSTL15
+    loc:
+       - N2
+       - K2
+       - M3
+       - K3
+       - M4
+       - L1
+       - L4
+       - K4
+       - K1
+       - J4
+       - F5
+       - G4
+       - E4
+       - D4
+       - F4 
+  FIXED_IO_ps_porb:
+    iostd: LVCMOS33
+    loc: C7
+  FIXED_IO_ps_srstb:
+    iostd: LVCMOS33
+    loc: B10
+  FIXED_IO_ps_clk:
+    iostd: LVCMOS33
+    loc: E7
+
 
 
 

jasper_library/platforms/red_pitaya_14.yaml

@@ -138,6 +138,137 @@ pins:
   DAC_IQRESET:
     iostd: LVCMOS33
     loc: N15
+  FIXED_IO_ddr_vrp:
+    iostd: SSTL15_T_DCI
+    loc: H5
+  FIXED_IO_ddr_vrn:
+    iostd: SSTL15_T_DCI
+    loc: G5
+  DDR_we_n:
+    iostd: SSTL15
+    loc: M5
+  DDR_RAS_n:
+    iostd: SSTL15
+    loc: P4
+  DDR_ODT:
+    iostd: SSTL15
+    loc: N5
+  DDR_reset_n:
+    iostd: SSTL15
+    loc: B4
+  DDR_DQS_p:
+    iostd: DIFF_SSTL15_T_DCI
+    loc:
+       - C2
+       - G2
+       - R2
+       - W5
+  DDR_DQS_n:
+    iostd: DIFF_SSTL15_T_DCI
+    loc:
+       - B2
+       - F2
+       - T2
+       - W4
+  DDR_DQ:
+    iostd: SSTL15_T_DCI
+    loc:
+       - C3
+       - B3
+       - A2
+       - A4
+       - D3
+       - D1
+       - C1
+       - E1
+       - E2
+       - E3
+       - G3
+       - H3
+       - J3
+       - H2
+       - H1
+       - J1
+       - P1
+       - P3
+       - R3
+       - R1
+       - T4
+       - U4
+       - U2
+       - U3
+       - V1
+       - Y3
+       - W1
+       - Y4
+       - Y2
+       - W3
+       - V2
+       - V3
+  DDR_DM:
+    iostd: DIFF_SSTL15_T_DCI
+    loc:
+       - A1
+       - F1
+       - T1
+       - Y1
+  DDR_CS_n:
+    iostd: SSTL15
+    loc: N1
+  DDR_CKE:
+    iostd: SSTL15
+    loc: N3
+  DDR_Ck_p:
+    iostd: SSTL15
+    loc: L2
+  DDR_Ck_n:
+    iostd: SSTL15
+    loc: M2
+  DDR_CAS_n:
+    iostd: SSTL15
+    loc: P5
+  DDR_ba:
+    iostd: DIFF_SSTL15
+    loc:
+       - L5
+       - R4
+       - J5
+  DDR_Addr:
+    iostd: SSTL15
+    loc:
+       - N2
+       - K2
+       - M3
+       - K3
+       - M4
+       - L1
+       - L4
+       - K4
+       - K1
+       - J4
+       - F5
+       - G4
+       - E4
+       - D4
+       - F4
+  FIXED_IO_ps_porb:
+    iostd: LVCMOS33
+    loc: C7
+  FIXED_IO_ps_srstb:
+    iostd: LVCMOS33
+    loc: B10
+  FIXED_IO_ps_clk:
+    iostd: LVCMOS33
+    loc: E7
+
+
+
+
+
+
+
+
+