Changes

examples/device-dashboard/net.c

@@ -56,14 +56,14 @@ uint64_t mg_now(void) {
 int ui_event_next(int no, struct ui_event *e) {
   if (no < 0 || no >= MAX_EVENTS_NO) return 0;
 
-  srand(no);
+  srand((unsigned) no);
   e->type = (uint8_t) rand() % 4;
   e->prio = (uint8_t) rand() % 3;
   e->timestamp =
-      (unsigned long) (mg_now() - 86400 * 1000 /* one day back */ +
+      (unsigned long) ((int64_t) mg_now() - 86400 * 1000 /* one day back */ +
                        no * 300 * 1000 /* 5 mins between alerts */ +
                        1000 * (rand() % 300) /* randomize event time */) /
-      1000;
+      1000UL;
 
   mg_snprintf(e->text, MAX_EVENT_TEXT_SIZE, "event#%d", no);
   return no + 1;
@@ -163,7 +163,7 @@ static void handle_stats_get(struct mg_connection *c) {
 static size_t print_events(void (*out)(char, void *), void *ptr, va_list *ap) {
   size_t len = 0;
   struct ui_event ev;
-  int pageno = va_arg(*ap, unsigned);
+  int pageno = va_arg(*ap, int);
   int no = (pageno - 1) * EVENTS_PER_PAGE;
   int end = no + EVENTS_PER_PAGE;
 

examples/microchip/same54/Makefile

@@ -11,7 +11,7 @@ SOURCES = main.c syscalls.c startup.c
 #SOURCES += cmsis_sam/xc32/ATSAME54P20A/startup_atsame54p20a.c
 
 SOURCES += mongoose.c net.c packed_fs.c
-CFLAGS += -DMG_ENABLE_TCPIP=1 -DMG_ARCH=MG_ARCH_NEWLIB -DMG_ENABLE_CUSTOM_MILLIS=1 -DMG_ENABLE_LINES=1
+CFLAGS += -DMG_ENABLE_TCPIP=1 -DMG_ARCH=MG_ARCH_NEWLIB -DMG_ENABLE_CUSTOM_MILLIS=1 #-DMG_ENABLE_LINES=1
 CFLAGS += -DMG_ENABLE_DRIVER_SAME54=1 -DMG_ENABLE_CUSTOM_RANDOM=1 -DMG_ENABLE_PACKED_FS=1 $(CFLAGS_EXTRA)
 
 VCON_API_KEY=IBrJL5K4arSGMiAXbUKWdG6I2gM

examples/microchip/same54/hal.h

@@ -194,9 +194,9 @@ static inline void ethernet_init(void) {
     PORT_REGS->GROUP[bank].PORT_PINCFG[no] |= PORT_PINCFG_PMUXEN_Msk;
     volatile uint8_t *m = &PORT_REGS->GROUP[bank].PORT_PMUX[no / 2], v = m[0];
     if (no & 1) {
-      m[0] = (uint8_t) (v & ~0xf0) | PORT_PMUX_PMUXO(af[i]);
+      m[0] = (uint8_t) ((v & ~0xf0) | PORT_PMUX_PMUXO(af[i]));
     } else {
-      m[0] = (uint8_t) (v & ~0x0f) | PORT_PMUX_PMUXE(af[i]);
+      m[0] = (uint8_t) ((v & ~0x0f) | PORT_PMUX_PMUXE(af[i]));
     }
   }
 

examples/microchip/same54/main.c

@@ -39,7 +39,8 @@ static void timer_fn(void *arg) {
 
 static void fn(struct mg_connection *c, int ev, void *ev_data, void *fn_data) {
   if (ev == MG_EV_HTTP_MSG) mg_http_reply(c, 200, "", "ok\n");
-  }
+  (void) ev_data, (void) fn_data;
+}
 
 int main(void) {
   gpio_input(BUTTON_PIN);
@@ -72,7 +73,7 @@ int main(void) {
 
   MG_INFO(("Initialising application..."));
   mg_http_listen(&mgr, "http://0.0.0.0", fn, NULL);
-  //web_init(&mgr);
+  // web_init(&mgr);
 
   MG_INFO(("Starting event loop"));
   for (;;) {

mongoose.c

@@ -7043,8 +7043,8 @@ struct mg_tcpip_driver mg_tcpip_driver_imxrt1020 = {
 #define ETH_DESC_CNT 4     // Descriptors count
 #define ETH_DS 2           // Descriptor size (words)
 
-static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] __attribute__((aligned(8)));
-static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] __attribute__((aligned(8)));
+static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE];
+static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE];
 static uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS];  // RX descriptors
 static uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS];  // TX descriptors
 static uint8_t s_txno;                           // Current TX descriptor
@@ -7082,52 +7082,42 @@ static bool mg_tcpip_driver_same54_init(struct mg_tcpip_if *ifp) {
   GMAC_REGS->GMAC_NCR = 0;                            // Disable RX & TX
   GMAC_REGS->GMAC_NCR |= GMAC_NCR_MPE_Msk;            // Enable MDC & MDIO
 
-  // Init TX descriptors
-  for (int i = 0; i < ETH_DESC_CNT; i++) {
+  for (int i = 0; i < ETH_DESC_CNT; i++) {   // Init TX descriptors
     s_txdesc[i][0] = (uint32_t) s_txbuf[i];  // Point to data buffer
     s_txdesc[i][1] = BIT(31);                // OWN bit
   }
   s_txdesc[ETH_DESC_CNT - 1][1] |= BIT(30);  // Last tx descriptor - wrap
 
-  // Init RX descriptors
-  for (int i = 0; i < ETH_DESC_CNT; i++) {
-    s_rxdesc[i][0] = (uint32_t) s_rxbuf[i];  // Address of the data buffer
-    s_rxdesc[i][1] = 0;                      // Clear status
+  GMAC_REGS->GMAC_DCFGR = GMAC_DCFGR_DRBS(0x18);  // DMA recv buf 1536
+  for (int i = 0; i < ETH_DESC_CNT; i++) {        // Init RX descriptors
+    s_rxdesc[i][0] = (uint32_t) s_rxbuf[i];       // Address of the data buffer
+    s_rxdesc[i][1] = 0;                           // Clear status
   }
-  s_rxdesc[ETH_DESC_CNT - 1][0] |= BIT(1);  // Last rx descriptor
+  s_rxdesc[ETH_DESC_CNT - 1][0] |= BIT(1);  // Last rx descriptor - wrap
 
   GMAC_REGS->GMAC_TBQB = (uint32_t) s_txdesc;  // about the descriptor addresses
   GMAC_REGS->GMAC_RBQB = (uint32_t) s_rxdesc;  // Let the controller know
 
-  // Select RMII operation mode
-  GMAC_REGS->GMAC_UR &= ~GMAC_UR_MII_Msk;
+  GMAC_REGS->SA[0].GMAC_SAB =
+      MG_U32(ifp->mac[3], ifp->mac[2], ifp->mac[1], ifp->mac[0]);
+  GMAC_REGS->SA[0].GMAC_SAT = MG_U32(0, 0, ifp->mac[5], ifp->mac[4]);
 
-  // Configure the receive filter
+  GMAC_REGS->GMAC_UR &= ~GMAC_UR_MII_Msk;  // Disable MII, use RMII
   GMAC_REGS->GMAC_NCFGR |= GMAC_NCFGR_MAXFS_Msk | GMAC_NCFGR_MTIHEN_Msk |
-                           GMAC_NCFGR_SPD_Msk | GMAC_NCFGR_FD_Msk;
-
-  // Clear transmit status register
+                           GMAC_NCFGR_SPD_Msk | GMAC_NCFGR_FD_Msk |
+                           GMAC_NCFGR_EFRHD_Msk | GMAC_NCFGR_CAF_Msk;
   GMAC_REGS->GMAC_TSR = GMAC_TSR_HRESP_Msk | GMAC_TSR_UND_Msk |
                         GMAC_TSR_TXCOMP_Msk | GMAC_TSR_TFC_Msk |
                         GMAC_TSR_TXGO_Msk | GMAC_TSR_RLE_Msk |
                         GMAC_TSR_COL_Msk | GMAC_TSR_UBR_Msk;
-
-  // Clear receive status register
   GMAC_REGS->GMAC_RSR = GMAC_RSR_HNO_Msk | GMAC_RSR_RXOVR_Msk |
                         GMAC_RSR_REC_Msk | GMAC_RSR_BNA_Msk;
-
-  // First disable all GMAC interrupts
-  GMAC_REGS->GMAC_IDR = ~0U;
-
-  // Only the desired ones are enabled
+  GMAC_REGS->GMAC_IDR = ~0U;  // Disable interrupts, then enable required
   GMAC_REGS->GMAC_IER = GMAC_IER_HRESP_Msk | GMAC_IER_ROVR_Msk |
                         GMAC_IER_TCOMP_Msk | GMAC_IER_TFC_Msk |
                         GMAC_IER_RLEX_Msk | GMAC_IER_TUR_Msk |
                         GMAC_IER_RXUBR_Msk | GMAC_IER_RCOMP_Msk;
-
-  // Enable the GMAC to transmit and receive data
   GMAC_REGS->GMAC_NCR |= GMAC_NCR_TXEN_Msk | GMAC_NCR_RXEN_Msk;
-
   NVIC_EnableIRQ(GMAC_IRQn);
 
   return true;
@@ -7167,12 +7157,12 @@ void GMAC_Handler(void) {
   uint32_t isr = GMAC_REGS->GMAC_ISR;
   uint32_t rsr = GMAC_REGS->GMAC_RSR;
   uint32_t tsr = GMAC_REGS->GMAC_TSR;
-  // MG_INFO(("ISR: 0x%x, TSR: 0x%x, RSR: 0x%x", isr, tsr, rsr));
-  if (isr & BIT(1)) {
-    if (rsr & BIT(1)) {
-      for (int i = 0; i < 10; i++) {
+  //MG_INFO(("ISR: 0x%x, TSR: 0x%x, RSR: 0x%x", isr, tsr, rsr));
+  if (isr & GMAC_ISR_RCOMP_Msk) {
+    if (rsr & GMAC_ISR_RCOMP_Msk) {
+      for (uint8_t i = 0; i < ETH_DESC_CNT; i++) {
         if ((s_rxdesc[s_rxno][0] & BIT(0)) == 0) break;
-        uint32_t len = s_rxdesc[s_rxno][1] & (BIT(14) - 1);
+        size_t len = s_rxdesc[s_rxno][1] & (BIT(13) - 1);
         mg_tcpip_qwrite(s_rxbuf[s_rxno], len, s_ifp);
         s_rxdesc[s_rxno][0] &= ~BIT(0);  // Disown
         if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0;
@@ -7183,8 +7173,7 @@ void GMAC_Handler(void) {
   if ((tsr & (GMAC_TSR_HRESP_Msk | GMAC_TSR_UND_Msk | GMAC_TSR_TXCOMP_Msk |
               GMAC_TSR_TFC_Msk | GMAC_TSR_TXGO_Msk | GMAC_TSR_RLE_Msk |
               GMAC_TSR_COL_Msk | GMAC_TSR_UBR_Msk)) != 0) {
-    GMAC_REGS->GMAC_TSR = tsr;
-    MG_INFO((" --> %#x %#x", s_txdesc[s_txno][1], tsr));
+    // MG_INFO((" --> %#x %#x", s_txdesc[s_txno][1], tsr));
     if (!(s_txdesc[s_txno][1] & BIT(31))) s_txdesc[s_txno][1] |= BIT(31);
   }
 
@@ -8824,6 +8813,7 @@ static void mg_tcpip_rx(struct mg_tcpip_if *ifp, void *buf, size_t len) {
   pkt.raw.ptr = (char *) buf;
   pkt.raw.len = len;
   pkt.eth = (struct eth *) buf;
+  //mg_hexdump(buf, len > 16 ? 16: len);
   if (pkt.raw.len < sizeof(*pkt.eth)) return;  // Truncated - runt?
   if (ifp->enable_mac_check &&
       memcmp(pkt.eth->dst, ifp->mac, sizeof(pkt.eth->dst)) != 0 &&

src/tcpip/driver_same54.c

@@ -11,8 +11,8 @@
 #define ETH_DESC_CNT 4     // Descriptors count
 #define ETH_DS 2           // Descriptor size (words)
 
-static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] __attribute__((aligned(8)));
-static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] __attribute__((aligned(8)));
+static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE];
+static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE];
 static uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS];  // RX descriptors
 static uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS];  // TX descriptors
 static uint8_t s_txno;                           // Current TX descriptor
@@ -50,52 +50,42 @@ static bool mg_tcpip_driver_same54_init(struct mg_tcpip_if *ifp) {
   GMAC_REGS->GMAC_NCR = 0;                            // Disable RX & TX
   GMAC_REGS->GMAC_NCR |= GMAC_NCR_MPE_Msk;            // Enable MDC & MDIO
 
-  // Init TX descriptors
-  for (int i = 0; i < ETH_DESC_CNT; i++) {
+  for (int i = 0; i < ETH_DESC_CNT; i++) {   // Init TX descriptors
     s_txdesc[i][0] = (uint32_t) s_txbuf[i];  // Point to data buffer
     s_txdesc[i][1] = BIT(31);                // OWN bit
   }
   s_txdesc[ETH_DESC_CNT - 1][1] |= BIT(30);  // Last tx descriptor - wrap
 
-  // Init RX descriptors
-  for (int i = 0; i < ETH_DESC_CNT; i++) {
-    s_rxdesc[i][0] = (uint32_t) s_rxbuf[i];  // Address of the data buffer
-    s_rxdesc[i][1] = 0;                      // Clear status
+  GMAC_REGS->GMAC_DCFGR = GMAC_DCFGR_DRBS(0x18);  // DMA recv buf 1536
+  for (int i = 0; i < ETH_DESC_CNT; i++) {        // Init RX descriptors
+    s_rxdesc[i][0] = (uint32_t) s_rxbuf[i];       // Address of the data buffer
+    s_rxdesc[i][1] = 0;                           // Clear status
   }
-  s_rxdesc[ETH_DESC_CNT - 1][0] |= BIT(1);  // Last rx descriptor
+  s_rxdesc[ETH_DESC_CNT - 1][0] |= BIT(1);  // Last rx descriptor - wrap
 
   GMAC_REGS->GMAC_TBQB = (uint32_t) s_txdesc;  // about the descriptor addresses
   GMAC_REGS->GMAC_RBQB = (uint32_t) s_rxdesc;  // Let the controller know
 
-  // Select RMII operation mode
-  GMAC_REGS->GMAC_UR &= ~GMAC_UR_MII_Msk;
+  GMAC_REGS->SA[0].GMAC_SAB =
+      MG_U32(ifp->mac[3], ifp->mac[2], ifp->mac[1], ifp->mac[0]);
+  GMAC_REGS->SA[0].GMAC_SAT = MG_U32(0, 0, ifp->mac[5], ifp->mac[4]);
 
-  // Configure the receive filter
+  GMAC_REGS->GMAC_UR &= ~GMAC_UR_MII_Msk;  // Disable MII, use RMII
   GMAC_REGS->GMAC_NCFGR |= GMAC_NCFGR_MAXFS_Msk | GMAC_NCFGR_MTIHEN_Msk |
-                           GMAC_NCFGR_SPD_Msk | GMAC_NCFGR_FD_Msk;
-
-  // Clear transmit status register
+                           GMAC_NCFGR_SPD_Msk | GMAC_NCFGR_FD_Msk |
+                           GMAC_NCFGR_EFRHD_Msk | GMAC_NCFGR_CAF_Msk;
   GMAC_REGS->GMAC_TSR = GMAC_TSR_HRESP_Msk | GMAC_TSR_UND_Msk |
                         GMAC_TSR_TXCOMP_Msk | GMAC_TSR_TFC_Msk |
                         GMAC_TSR_TXGO_Msk | GMAC_TSR_RLE_Msk |
                         GMAC_TSR_COL_Msk | GMAC_TSR_UBR_Msk;
-
-  // Clear receive status register
   GMAC_REGS->GMAC_RSR = GMAC_RSR_HNO_Msk | GMAC_RSR_RXOVR_Msk |
                         GMAC_RSR_REC_Msk | GMAC_RSR_BNA_Msk;
-
-  // First disable all GMAC interrupts
-  GMAC_REGS->GMAC_IDR = ~0U;
-
-  // Only the desired ones are enabled
+  GMAC_REGS->GMAC_IDR = ~0U;  // Disable interrupts, then enable required
   GMAC_REGS->GMAC_IER = GMAC_IER_HRESP_Msk | GMAC_IER_ROVR_Msk |
                         GMAC_IER_TCOMP_Msk | GMAC_IER_TFC_Msk |
                         GMAC_IER_RLEX_Msk | GMAC_IER_TUR_Msk |
                         GMAC_IER_RXUBR_Msk | GMAC_IER_RCOMP_Msk;
-
-  // Enable the GMAC to transmit and receive data
   GMAC_REGS->GMAC_NCR |= GMAC_NCR_TXEN_Msk | GMAC_NCR_RXEN_Msk;
-
   NVIC_EnableIRQ(GMAC_IRQn);
 
   return true;
@@ -135,12 +125,12 @@ void GMAC_Handler(void) {
   uint32_t isr = GMAC_REGS->GMAC_ISR;
   uint32_t rsr = GMAC_REGS->GMAC_RSR;
   uint32_t tsr = GMAC_REGS->GMAC_TSR;
-  MG_INFO(("ISR: 0x%x, TSR: 0x%x, RSR: 0x%x", isr, tsr, rsr));
-  if (isr & BIT(1)) {
-    if (rsr & BIT(1)) {
-      for (int i = 0; i < 10; i++) {
+  //MG_INFO(("ISR: 0x%x, TSR: 0x%x, RSR: 0x%x", isr, tsr, rsr));
+  if (isr & GMAC_ISR_RCOMP_Msk) {
+    if (rsr & GMAC_ISR_RCOMP_Msk) {
+      for (uint8_t i = 0; i < ETH_DESC_CNT; i++) {
         if ((s_rxdesc[s_rxno][0] & BIT(0)) == 0) break;
-        uint32_t len = s_rxdesc[s_rxno][1] & (BIT(14) - 1);
+        size_t len = s_rxdesc[s_rxno][1] & (BIT(13) - 1);
         mg_tcpip_qwrite(s_rxbuf[s_rxno], len, s_ifp);
         s_rxdesc[s_rxno][0] &= ~BIT(0);  // Disown
         if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0;
@@ -151,8 +141,7 @@ void GMAC_Handler(void) {
   if ((tsr & (GMAC_TSR_HRESP_Msk | GMAC_TSR_UND_Msk | GMAC_TSR_TXCOMP_Msk |
               GMAC_TSR_TFC_Msk | GMAC_TSR_TXGO_Msk | GMAC_TSR_RLE_Msk |
               GMAC_TSR_COL_Msk | GMAC_TSR_UBR_Msk)) != 0) {
-    GMAC_REGS->GMAC_TSR = tsr;
-    MG_INFO((" --> %#x %#x", s_txdesc[s_txno][1], tsr));
+    // MG_INFO((" --> %#x %#x", s_txdesc[s_txno][1], tsr));
     if (!(s_txdesc[s_txno][1] & BIT(31))) s_txdesc[s_txno][1] |= BIT(31);
   }
 

src/tcpip/tcpip.c

@@ -762,6 +762,7 @@ static void mg_tcpip_rx(struct mg_tcpip_if *ifp, void *buf, size_t len) {
   pkt.raw.ptr = (char *) buf;
   pkt.raw.len = len;
   pkt.eth = (struct eth *) buf;
+  //mg_hexdump(buf, len > 16 ? 16: len);
   if (pkt.raw.len < sizeof(*pkt.eth)) return;  // Truncated - runt?
   if (ifp->enable_mac_check &&
       memcmp(pkt.eth->dst, ifp->mac, sizeof(pkt.eth->dst)) != 0 &&