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Issues for 6LBR in Linux PC #2
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Hi, For your 3 points:
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hello,
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Hi, Sorry for deletion. However the problem was solved. Thanks for help. Currently trying to get it work on Ubuntu 10.04. |
No problem I was afraid I had deleted it myself with a missclick :) sudo apt-get install python2.7-pip sudo pip-2.7 install pyserial |
Solved in #3 |
…ia Z1). The following problems were present in the existing DCO calibration algorithm: Problem #1. In function msp430_quick_synch_dco(), the "for(i=0; i < 1000; i++) { .. }" loop is optimized away by the compiler, as i is not volatile. Making i volatile would improve the results, but would not be sufficient: see the next point. Problem #2. According to MSP430F2617 Device Erratasheet, bug BCL12 precludes a naive implementations of "fast" calibration altogether. The bug is present on all MCU revisions up to date. The description of the bug: "After switching RSELx bits (located in register BCSCTL1) from a value of >13 to a value of <12 OR from a value of <12 to a value of >13, the resulting clock delivered by the DCO can stop before the new clock frequency is applied. This dead time is approximately 20 us. In some instances, the DCO may completely stop, requiring a power cycle. Furthermore, if all of the RSELx bits in the BSCTL1 register are set, modifying the DCOCTL register to change the DCOx or the MODx bits could also result in DCO dead time or DCO hang up." In Contiki code for msp430f2xxx @ 8MHz, the RSEL search currently typically goes from 15 down to 11, thus violating the rules. Step-by-step RSEL change is proposed as the best possible workaround: "[..] more reliable method can be implemented by changing the RSEL bits step by step in order to guarantee safe function without any dead time of the DCO." Problem #3. The old Contiki code started from the highest possible calibration values: RSEL=15, DCOx=7. According to MSP430F2617 datasheet, this means that the DCO frequency is set to 26 MHz. For one, Vcc under 3V is not supported for this frequency, so this means that battery-powered nodes have a big problem. The minimal operating voltages are: - 1.8V for RSEL <= 13 - 2.2V for RSEL = 14 - 3.0V for RSEL = 15 So the correct way is to always start calibration from RSEL <= 13, unless explicityly pre-calibred values are present. Problem #4. Timer B should be turned off after the calibration, following the "Principles for Low-Power Applications" in MSP430 user's Guide. The patch fixes these issues by performing step-by-step calibration and turning off Timer B afterwards. As opposed to MSP430F1xxx calibration, this algorithm does not change the ACLK divider beforehand; attempts to make calibration more precise would lead to looping in some cases, as the calibration step granularity at larger frequencies is quite big. Additionally, the patch improves DCOSYNCH_CONF_ENABLED behavior, allowing the resynchronization to correct for more than one step.
Add antenna configuration functionality and a small fix to the button sensor.
A delay of 1 ms must be added after the System Reset Command. Still wait for ESTAT.CLKRDY afterwards as a precaution. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
The Programmable Interrupt Controller is a chip responsible for translating hardware interrupts to system interrupts. When it receives an Interrupt Request (IRQ), it triggers the appropriate interrupt line reaching the appropriate IDT gate, following a previously setup offset. There are 2 daisy-chained PICs. PIC1 handles IRQs 0-7 and PIC2 handles IRQs 8-15. If no vector offset is set, an IRQ0, for instance, would trigger the interrupt 0, clashing with the "Division by zero exception" handler. Thus the IRQs must be remapped. This patch implements the PICs initialization through their 4 Initialization Command Words (ICWs) in a very "canonical" way: - ICW1: the initializing command; - ICW2: the vector offset for the PIC1 and PIC2 (we add an offset of 32 positions); - ICW3: the inter-PICs wiring setup (we connect PIC2 to PIC1's IRQ2); - ICW4: extra systems information (we set PIC1 as Master and PIC2 as slave). It then masks the Interrupt Mask Register, blocking all IRQs but #2 initially. These must be unmasked on demand. The IMR is 8-bits long, so setting the n^th bit to 1 would DISABLE the IRQ n while setting it to 0 would ENABLE IRQ n. As stated, this is an implementation of the legacy 8259 PIC. More investigation is needed so we decide if it is enough or if we need the (newer) APIC implementation instead. This patch also adds the outb() helper function to helpers.h. The helpers is a wrapper for assembly 'out' instruction. Finally, since we now properly support hardware interrupts, this patch also enables IRQs in platform main(). More information: - Quark X1000 Datasheet, section 21.12, page 898. - http://wiki.osdev.org/8259_PIC - http://stanislavs.org/helppc/8259.html
Dear developers,
Thank you.
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