The vivado path changes and vendor primitive fix. (#46)

* Fixed VHDL conversion via rhea.build.toolflow.convert, fixed a typo, fixed spacing

* Added 'ticks' property to Clock() to retrieve the ratio of the clocks ticks to simulation ticks

* Added Clock.delay() to allow for easy delaying for a certain number of ticks of user clock signals

* Parameter checking and setting ticks when hticks is overridden in Clock.gen()

* Whitespace and @todo comment / question

* Removed a comment and delay()

* Fix for #41, escapes backspaces as well as quoting file paths (so paths with spaces in them will also work

* Fix for Vivado 2016.2 toolchain not launching on Windows 10.   (Needed to specify full binary 'vivado.bat' for windows to find it)

* Changed quoting style per @cfelton's request

* Initial definitions for Digilent CModA7_15T & CModA7_35T

* Added uart to cmoda7, and commented in remaining constraints for future reference

* Added pmod_je (standard pmod) definition to zybo board.  Hardware verified

* Added cellular ram part reference and datasheet link

* enable zybo in build make file

* the verilog_code needs to be attached to a block before it is instantiated

examples/boards/zybo/blinky.py

@@ -1,9 +1,11 @@
 
+import myhdl
 from myhdl import (Signal, intbv, always_seq, always_comb, concat)
 
 from rhea.build.boards import get_board
 
 
+@myhdl.block
 def zybo_blink(led, btn, clock):
     maxcnt = int(clock.frequency)
     cnt = Signal(intbv(0, min=0, max=maxcnt))

examples/build/Makefile

@@ -23,15 +23,15 @@ anvyl: #xilinx/anvyl.bit
 mojo: #xilinx/anvyl.bit
 	time $(PYTHON) ex_mojo.py
 
-#atlys: #xilinx/atlys.bit
-#	$(PYTHON) ex_atlys.py
+# atlys: #xilinx/atlys.bit
+# 	$(PYTHON) ex_atlys.py
 
-#zybo: #xilinx/zybo.bit
-#	$(PYTHON) ex_zybo.py
+zybo: #xilinx/zybo.bit
+	$(PYTHON) ex_zybo.py
 
 
-#parallela: #xilinx/parallela.bit
-#	$(PYTHON) ex_parallela.py
+# parallela: #xilinx/parallela.bit
+# 	$(PYTHON) ex_parallela.py
 
 
 #########################################################

rhea/build/boards/get_board.py

@@ -9,7 +9,7 @@
 from .xilinx import (Anvyl, Atlys, Mojo, Nexys, NexysVideo, Parallella,
                      PapilioOne, PapilioPro, SX1, UFO400, Waxwing45,
                      Waxwing45carrier, Xula, Xula2, Xula2StickItMB,
-                     XUPV2P, Zybo)
+                     XUPV2P, Zybo, CModA7_15T, CModA7_35T)
 from .altera import (DE0Nano, DE0NanoSOC, DE0CV, DE1SOC)
 from .lattice import (Icestick, CATBoard)
 
@@ -20,7 +20,8 @@
         'ufo400': UFO400, 'waxwing45': Waxwing45,
         'waxwing45carrier': Waxwing45carrier, 'xula': Xula,
         'xula2': Xula2, 'xula2_stickit_mb': Xula2StickItMB,
-        'xupv2p': XUPV2P, 'zybo': Zybo, 
+        'xupv2p': XUPV2P, 'zybo': Zybo, 'cmoda7_15t': CModA7_15T,
+        'cmoda7_35t': CModA7_35T,
         }
 
 abrd = {'de0nano': DE0Nano, 'de0nano_soc': DE0NanoSOC, 'de0cv': DE0CV, 

rhea/build/boards/xilinx/__init__.py

@@ -16,3 +16,4 @@
 from ._xula import XulaStickItMB, Xula2StickItMB
 from ._xupv2p import XUPV2P
 from .zybo import Zybo
+from .cmoda7 import CModA7_15T, CModA7_35T

rhea/build/boards/xilinx/cmoda7.py

@@ -0,0 +1,154 @@
+# Digilent CModA7, 15T & 35T variants.
+#
+# Reference Manual:
+#   https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/reference-manual
+#
+# Master Constraints File:
+#   https://raw.githubusercontent.com/Digilent/CmodA7/master/Resources/XDC/CmodA7_Master.xdc
+
+
+from rhea.build import FPGA
+from rhea.build.toolflow import ISE 
+from rhea.build.toolflow import Vivado
+
+
+class CModA7(FPGA):
+    vendor = 'xilinx'
+    family = 'artix'
+    package = 'CPG236'
+    speed = -1
+    _name = 'cmoda7'
+
+
+    default_clocks = {
+        'clock': dict(frequency=12e6, pins=('L17',), iostandard='LVCMOS33')
+    }
+
+    default_ports = {
+        # leds
+        'led': dict(pins=('A17', 'C16',), iostandard='LVCMOS33'),
+        'led0_b': dict(pins=('B17',), iostandard='LVCMOS33'),
+        'led0_g': dict(pins=('B16',), iostandard='LVCMOS33'),
+        'led0_r': dict(pins=('C17',), iostandard='LVCMOS33'),
+
+        # buttons
+        'btn': dict(pins=('A18','B17',), iostandard='LVCMOS33'),
+
+        # pmod header ja
+        'pmod_ja': dict(pins=('G17', 'G19', 'N18', 'L18',
+                              'H17', 'H19', 'J19', 'K18',),
+                        iostandard="LVCMOS33"),
+
+        # analog xadc pins
+        ## Only declare these if you want to use pins 15 and 16 as single ended analog inputs. pin 15 -> vaux4, pin16 -> vaux12
+        # set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ain_n[15]
+        # set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L1P_T0_AD4P_35 Sch=ain_p[15]
+        # set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L2N_T0_AD12N_35 Sch=ain_n[16]
+        # set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L2P_T0_AD12P_35 Sch=ain_p[16]
+
+        # gpio pins
+        ## Pins 15 and 16 should remain commented if using them as analog inputs
+        # set_property -dict { PACKAGE_PIN M3    IOSTANDARD LVCMOS33 } [get_ports { pio[01] }]; #IO_L8N_T1_AD14N_35 Sch=pio[01]
+        # set_property -dict { PACKAGE_PIN L3    IOSTANDARD LVCMOS33 } [get_ports { pio[02] }]; #IO_L8P_T1_AD14P_35 Sch=pio[02]
+        # set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports { pio[03] }]; #IO_L12P_T1_MRCC_16 Sch=pio[03]
+        # set_property -dict { PACKAGE_PIN K3    IOSTANDARD LVCMOS33 } [get_ports { pio[04] }]; #IO_L7N_T1_AD6N_35 Sch=pio[04]
+        # set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { pio[05] }]; #IO_L11P_T1_SRCC_16 Sch=pio[05]
+        # set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { pio[06] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=pio[06]
+        # set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33 } [get_ports { pio[07] }]; #IO_L6N_T0_VREF_16 Sch=pio[07]
+        # set_property -dict { PACKAGE_PIN B15   IOSTANDARD LVCMOS33 } [get_ports { pio[08] }]; #IO_L11N_T1_SRCC_16 Sch=pio[08]
+        # set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { pio[09] }]; #IO_L6P_T0_16 Sch=pio[09]
+        # set_property -dict { PACKAGE_PIN J3    IOSTANDARD LVCMOS33 } [get_ports { pio[10] }]; #IO_L7P_T1_AD6P_35 Sch=pio[10]
+        # set_property -dict { PACKAGE_PIN J1    IOSTANDARD LVCMOS33 } [get_ports { pio[11] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=pio[11]
+        # set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { pio[12] }]; #IO_L5P_T0_AD13P_35 Sch=pio[12]
+        # set_property -dict { PACKAGE_PIN L1    IOSTANDARD LVCMOS33 } [get_ports { pio[13] }]; #IO_L6N_T0_VREF_35 Sch=pio[13]
+        # set_property -dict { PACKAGE_PIN L2    IOSTANDARD LVCMOS33 } [get_ports { pio[14] }]; #IO_L5N_T0_AD13N_35 Sch=pio[14]
+        # set_property -dict { PACKAGE_PIN M1    IOSTANDARD LVCMOS33 } [get_ports { pio[17] }]; #IO_L9N_T1_DQS_AD7N_35 Sch=pio[17]
+        # set_property -dict { PACKAGE_PIN N3    IOSTANDARD LVCMOS33 } [get_ports { pio[18] }]; #IO_L12P_T1_MRCC_35 Sch=pio[18]
+        # set_property -dict { PACKAGE_PIN P3    IOSTANDARD LVCMOS33 } [get_ports { pio[19] }]; #IO_L12N_T1_MRCC_35 Sch=pio[19]
+        # set_property -dict { PACKAGE_PIN M2    IOSTANDARD LVCMOS33 } [get_ports { pio[20] }]; #IO_L9P_T1_DQS_AD7P_35 Sch=pio[20]
+        # set_property -dict { PACKAGE_PIN N1    IOSTANDARD LVCMOS33 } [get_ports { pio[21] }]; #IO_L10N_T1_AD15N_35 Sch=pio[21]
+        # set_property -dict { PACKAGE_PIN N2    IOSTANDARD LVCMOS33 } [get_ports { pio[22] }]; #IO_L10P_T1_AD15P_35 Sch=pio[22]
+        # set_property -dict { PACKAGE_PIN P1    IOSTANDARD LVCMOS33 } [get_ports { pio[23] }]; #IO_L19N_T3_VREF_35 Sch=pio[23]
+        # set_property -dict { PACKAGE_PIN R3    IOSTANDARD LVCMOS33 } [get_ports { pio[26] }]; #IO_L2P_T0_34 Sch=pio[26]
+        # set_property -dict { PACKAGE_PIN T3    IOSTANDARD LVCMOS33 } [get_ports { pio[27] }]; #IO_L2N_T0_34 Sch=pio[27]
+        # set_property -dict { PACKAGE_PIN R2    IOSTANDARD LVCMOS33 } [get_ports { pio[28] }]; #IO_L1P_T0_34 Sch=pio[28]
+        # set_property -dict { PACKAGE_PIN T1    IOSTANDARD LVCMOS33 } [get_ports { pio[29] }]; #IO_L3P_T0_DQS_34 Sch=pio[29]
+        # set_property -dict { PACKAGE_PIN T2    IOSTANDARD LVCMOS33 } [get_ports { pio[30] }]; #IO_L1N_T0_34 Sch=pio[30]
+        # set_property -dict { PACKAGE_PIN U1    IOSTANDARD LVCMOS33 } [get_ports { pio[31] }]; #IO_L3N_T0_DQS_34 Sch=pio[31]
+        # set_property -dict { PACKAGE_PIN W2    IOSTANDARD LVCMOS33 } [get_ports { pio[32] }]; #IO_L5N_T0_34 Sch=pio[32]
+        # set_property -dict { PACKAGE_PIN V2    IOSTANDARD LVCMOS33 } [get_ports { pio[33] }]; #IO_L5P_T0_34 Sch=pio[33]
+        # set_property -dict { PACKAGE_PIN W3    IOSTANDARD LVCMOS33 } [get_ports { pio[34] }]; #IO_L6N_T0_VREF_34 Sch=pio[34]
+        # set_property -dict { PACKAGE_PIN V3    IOSTANDARD LVCMOS33 } [get_ports { pio[35] }]; #IO_L6P_T0_34 Sch=pio[35]
+        # set_property -dict { PACKAGE_PIN W5    IOSTANDARD LVCMOS33 } [get_ports { pio[36] }]; #IO_L12P_T1_MRCC_34 Sch=pio[36]
+        # set_property -dict { PACKAGE_PIN V4    IOSTANDARD LVCMOS33 } [get_ports { pio[37] }]; #IO_L11N_T1_SRCC_34 Sch=pio[37]
+        # set_property -dict { PACKAGE_PIN U4    IOSTANDARD LVCMOS33 } [get_ports { pio[38] }]; #IO_L11P_T1_SRCC_34 Sch=pio[38]
+        # set_property -dict { PACKAGE_PIN V5    IOSTANDARD LVCMOS33 } [get_ports { pio[39] }]; #IO_L16N_T2_34 Sch=pio[39]
+        # set_property -dict { PACKAGE_PIN W4    IOSTANDARD LVCMOS33 } [get_ports { pio[40] }]; #IO_L12N_T1_MRCC_34 Sch=pio[40]
+        # set_property -dict { PACKAGE_PIN U5    IOSTANDARD LVCMOS33 } [get_ports { pio[41] }]; #IO_L16P_T2_34 Sch=pio[41]
+        # set_property -dict { PACKAGE_PIN U2    IOSTANDARD LVCMOS33 } [get_ports { pio[42] }]; #IO_L9N_T1_DQS_34 Sch=pio[42]
+        # set_property -dict { PACKAGE_PIN W6    IOSTANDARD LVCMOS33 } [get_ports { pio[43] }]; #IO_L13N_T2_MRCC_34 Sch=pio[43]
+        # set_property -dict { PACKAGE_PIN U3    IOSTANDARD LVCMOS33 } [get_ports { pio[44] }]; #IO_L9P_T1_DQS_34 Sch=pio[44]
+        # set_property -dict { PACKAGE_PIN U7    IOSTANDARD LVCMOS33 } [get_ports { pio[45] }]; #IO_L19P_T3_34 Sch=pio[45]
+        # set_property -dict { PACKAGE_PIN W7    IOSTANDARD LVCMOS33 } [get_ports { pio[46] }]; #IO_L13P_T2_MRCC_34 Sch=pio[46]
+        # set_property -dict { PACKAGE_PIN U8    IOSTANDARD LVCMOS33 } [get_ports { pio[47] }]; #IO_L14P_T2_SRCC_34 Sch=pio[47]
+        # set_property -dict { PACKAGE_PIN V8    IOSTANDARD LVCMOS33 } [get_ports { pio[48] }]; #IO_L14N_T2_SRCC_34 Sch=pio[48]
+
+        # uart
+        'uart_rxd_out': dict(pins=('J18',), iostandard='LVCMOS33'),
+        'uart_txd_in': dict(pins=('J17',), iostandard='LVCMOS33'),
+
+        # crypto 1 wire interface
+        # set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_0_14 Sch=crypto_sda
+
+        # qspi
+        # set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { qspi_cs    }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
+        # set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+        # set_property -dict { PACKAGE_PIN D19   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+        # set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+
+        # cellular ram ( ISSI IS61WV5128BLL-10BLI - http://www.issi.com/WW/pdf/61-64WV5128Axx-Bxx.pdf )
+        # set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[0]  }]; #IO_L11P_T1_SRCC_14 Sch=sram- a[0]
+        # set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[1]  }]; #IO_L11N_T1_SRCC_14 Sch=sram- a[1]
+        # set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[2]  }]; #IO_L12N_T1_MRCC_14 Sch=sram- a[2]
+        # set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[3]  }]; #IO_L13P_T2_MRCC_14 Sch=sram- a[3]
+        # set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[4]  }]; #IO_L13N_T2_MRCC_14 Sch=sram- a[4]
+        # set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[5]  }]; #IO_L14P_T2_SRCC_14 Sch=sram- a[5]
+        # set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[6]  }]; #IO_L14N_T2_SRCC_14 Sch=sram- a[6]
+        # set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[7]  }]; #IO_L16N_T2_A15_D31_14 Sch=sram- a[7]
+        # set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[8]  }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sram- a[8]
+        # set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[9]  }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=sram- a[9]
+        # set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[10] }]; #IO_L16P_T2_CSI_B_14 Sch=sram- a[10]
+        # set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[11] }]; #IO_L17P_T2_A14_D30_14 Sch=sram- a[11]
+        # set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[12] }]; #IO_L17N_T2_A13_D29_14 Sch=sram- a[12]
+        # set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[13] }]; #IO_L18P_T2_A12_D28_14 Sch=sram- a[13]
+        # set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[14] }]; #IO_L18N_T2_A11_D27_14 Sch=sram- a[14]
+        # set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[15] }]; #IO_L19P_T3_A10_D26_14 Sch=sram- a[15]
+        # set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[16] }]; #IO_L20P_T3_A08_D24_14 Sch=sram- a[16]
+        # set_property -dict { PACKAGE_PIN W17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[17] }]; #IO_L20N_T3_A07_D23_14 Sch=sram- a[17]
+        # set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[18] }]; #IO_L21P_T3_DQS_14 Sch=sram- a[18]
+        # set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports { MemDB[0]   }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=sram-dq[0]
+        # set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { MemDB[1]   }]; #IO_L22P_T3_A05_D21_14 Sch=sram-dq[1]
+        # set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports { MemDB[2]   }]; #IO_L22N_T3_A04_D20_14 Sch=sram-dq[2]
+        # set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { MemDB[3]   }]; #IO_L23P_T3_A03_D19_14 Sch=sram-dq[3]
+        # set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { MemDB[4]   }]; #IO_L23N_T3_A02_D18_14 Sch=sram-dq[4]
+        # set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { MemDB[5]   }]; #IO_L24P_T3_A01_D17_14 Sch=sram-dq[5]
+        # set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { MemDB[6]   }]; #IO_L24N_T3_A00_D16_14 Sch=sram-dq[6]
+        # set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { MemDB[7]   }]; #IO_25_14 Sch=sram-dq[7]
+        # set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS33 } [get_ports { RamOEn     }]; #IO_L10P_T1_D14_14 Sch=sram-oe
+        # set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { RamWEn     }]; #IO_L10N_T1_D15_14 Sch=sram-we
+        # set_property -dict { PACKAGE_PIN N19   IOSTANDARD LVCMOS33 } [get_ports { RamCEn     }]; #IO_L9N_T1_DQS_D13_14 Sch=sram-ce
+
+    }
+
+    def get_flow(self, top=None):
+        return Vivado(brd=self, top=top)
+
+
+class CModA7_15T(CModA7):
+    _name = "cmoda7_15t"
+    device = 'XC7A15T'
+
+class CModA7_35T(CModA7):
+    _name = "cmoda7_35t"
+    device = 'XC7A35T'
+

rhea/build/boards/xilinx/zybo.py

@@ -45,6 +45,11 @@ class Zybo(FPGA):
                               'Y18', 'Y19', 'W18', 'W19',),
                         iostandard="LVDS_25"),
 
+        # je is the 'standard' pmod
+        'pmod_je': dict(pins=('V12', 'W16', 'J15', 'H15',
+                              'V13', 'U17', 'T17', 'Y17',),
+                        iostandard='LVCMOS33'),
+
         # VGA (names from the reference manual but lowercase and
         # with the "vga_" prefix)
         'vga_red': dict(pins=('M19', 'L20', 'J20', 'G20', 'F19',),

rhea/build/toolflow/convert.py

@@ -45,7 +45,7 @@ def convert(brd, top=None, name=None, use='verilog', path='.'):
         if name is not None:
             myhdl.toVHDL.name = name
         # myhdl.toVHDL(brd.top, **pp)
-        inst.convert(hdl='Verilog', name=name, testbench=False)
+        inst.convert(hdl='VHDL', name=name)
         brd.name = name
         brd.vfn = "%s.vhd"%(name)
     else:

rhea/build/toolflow/xilinx/vivado.py

@@ -8,6 +8,7 @@
 
 import sys
 import os
+import platform
 import shutil
 from time import gmtime, strftime
 
@@ -82,7 +83,12 @@ def create_constraints(self):
                 fid.write(line + '\n')
 
 
+    def escape_path(self, path):
+        # Vivado needs to have backslashes in it's tcl files escaped.
+        return path.replace('\\', '\\\\')
+
     def create_flow_script(self):
+
         fn = os.path.join(self.path, self.name+'.tcl')
 
         # start with the text string for the TCL script
@@ -92,12 +98,13 @@ def create_flow_script(self):
         tcl += ["# create: {}".format(date_time)]
         tcl += ["# by: {}".format(os.path.basename(sys.argv[0]))]
         tcl += ["#\n#\n"]
-        
+
         tcl += ["# set compile directory:"]
-        tcl += ["set origin_dir {}".format(".")]
+        tcl += ["set origin_dir \"{}\"".format(self.escape_path(self.path))]
 
-        tcl += ["create_project -force {} {}".format(
-            self.name, os.path.join(self.path, self.name))]
+        project_directory = self.escape_path(os.path.join(self.path, self.name))
+        tcl += ["create_project -force {} \"{}\"".format(
+            self.name, project_directory)]
         tcl += ["set proj_dir [get_property directory [current_project]]"]
         tcl += ["set obj [get_projects {}]".format(self.name)]
         brd = self.brd
@@ -106,20 +113,24 @@ def create_flow_script(self):
         tcl += ["set_property PART {} $obj".format(part)]
 
         # add HDL files
-        tcl += ["# create sources"]
+        tcl += [""]
+        tcl += ["# add sources"]
         for hdl_file in self._hdl_file_list:
-            tcl += ["add_files {}".format(os.path.join(self.path, hdl_file))]
+            tcl += ["add_files \"{}\"".format(self.escape_path(os.path.join(self.path, hdl_file)))]
+
+        tcl += ["read_xdc \"{}\"".format(self.escape_path(self.xdc_file))]
 
-        tcl += ["read_xdc {}".format(self.xdc_file)]
+        tcl += [""]
+        tcl += ["# build design"]
         synopts = ""
         tcl += ["synth_design -top {} {}".format(self.name, synopts)]
         tcl += ["opt_design"]
         tcl += ["place_design"]
         tcl += ["route_design"]
-        tcl += ["report_timing_summary -file {}".format(
-            os.path.join(self.path, self.name+'_timing.rpt'))]
-        tcl += ["write_bitstream -force {}".format(
-            os.path.join(self.path, self.name+'.bit'))]
+        tcl += ["report_timing_summary -file \"{}\"".format(
+            self.escape_path(os.path.join(self.path, self.name+'_timing.rpt')))]
+        tcl += ["write_bitstream -force \"{}\"".format(
+            self.escape_path(os.path.join(self.path, self.name+'.bit')))]
 
         tcl += ["quit"]
 
@@ -148,7 +159,11 @@ def run(self, use='verilog', name=None):
         self.add_files(cfiles)
         self.create_constraints()
         tcl_name = self.create_flow_script()
-        cmd = ['vivado', '-mode', 'batch', '-source', tcl_name]
+        binary_name = 'vivado'
+        if platform.system() == 'Windows':
+            binary_name += '.bat'
+
+        cmd = [binary_name, '-mode', 'batch', '-source', tcl_name]
         self.logfn = self._execute_flow(cmd, "build_vivado.log")
 
         # @todo: refactor into a cleanup function

rhea/cores/misc/timer_ticks.py

@@ -13,7 +13,7 @@ def timer_counter(glbl, counter, increment, overflow):
     @always_seq(clock.posedge, reset=reset)
     def beh_count():
         if increment:
-            if counter == count_max-1:
+            if counter == count_max - 1:
                 counter.next = 0
             else:
                 counter.next = counter + 1

rhea/cores/misc/uix/btn_mm_ctl.py

@@ -9,7 +9,7 @@
 @myhdl.block
 def button_controller(glbl, regbus, btns, led_addr=0x240):
     """ Generate bus cycles from a button input
-    This is a non-sensicle module that creates memory-mapped
+    This is a nonsensical module that creates memory-mapped
     bus cycles from a button press.  It is used in simple
     examples and demonstrations.
     """