Updated release notes

chipsalliance · Aug 13, 2019 · 189ce25 · 189ce25
1 parent 8242950
commit 189ce25
Showing 1 changed file with 3 additions and 2 deletions.
diff --git a/release-notes.md b/release-notes.md
@@ -4,13 +4,14 @@
     * The ebreak and ecall instructions are no longer counted in the MINSRET
 	  control and status register.
     * Write to SBDATA0 does not start SB write access when both
-	  sbreadonaddr/sbreadondata are zero.
+	  sbreadonaddr/sbreadondata are zero. This fixes issue number
+	  5 on github.
 
 1. FPGA support: Add fpga_optimize option to swerv.config which
    eliminates over 90% of clock-gating enabling faster FPGA
    simulation.
 
-1. Usability: Untabified all the verilog files.
+1. Usability: Untabified all the verilog files.  This fixes issue number 3 on github.
 
 # SweRV RISC-V Core<sup>TM</sup> 1.1 from Western Digital
 ## Release Notes