Merge pull request #151 from antmicro/gh-147

Export ICCM/DCCM ECC error signals

design/el2_veer.sv

@@ -377,6 +377,12 @@ import el2_pkg::*;
    input logic [31:0]           dmi_reg_wdata,             // write data
    output logic [31:0]          dmi_reg_rdata,
 
+   // ICCM/DCCM ECC status
+   output logic                 iccm_ecc_single_error,
+   output logic                 iccm_ecc_double_error,
+   output logic                 dccm_ecc_single_error,
+   output logic                 dccm_ecc_double_error,
+
    input logic [pt.PIC_TOTAL_INT:1]           extintsrc_req,
    input logic                   timer_int,
    input logic                   soft_int,
@@ -393,7 +399,11 @@ import el2_pkg::*;
 
    logic                         ifu_pmu_instr_aligned;
    logic                         ifu_ic_error_start;
+   logic                         ifu_iccm_dma_rd_ecc_single_err;
    logic                         ifu_iccm_rd_ecc_single_err;
+   logic                         ifu_iccm_rd_ecc_double_err;
+   logic                         lsu_dccm_rd_ecc_single_err;
+   logic                         lsu_dccm_rd_ecc_double_err;
 
    logic                         lsu_axi_awready_ahb;
    logic                         lsu_axi_wready_ahb;
@@ -895,6 +905,9 @@ import el2_pkg::*;
                             );
 
 
+   assign iccm_ecc_single_error = ifu_iccm_rd_ecc_single_err || ifu_iccm_dma_rd_ecc_single_err;
+   assign iccm_ecc_double_error = ifu_iccm_rd_ecc_double_err;
+
    el2_dec #(.pt(pt)) dec (
                             .clk(active_l2clk),
                             .dbg_cmd_wrdata(dbg_cmd_wrdata[1:0]),
@@ -932,6 +945,8 @@ import el2_pkg::*;
 
                             );
 
+   assign dccm_ecc_single_error = lsu_dccm_rd_ecc_single_err;
+   assign dccm_ecc_double_error = lsu_dccm_rd_ecc_double_err;
 
    el2_pic_ctrl  #(.pt(pt)) pic_ctrl_inst (
                                             .clk(free_l2clk),

design/el2_veer_wrapper.sv

@@ -291,6 +291,12 @@ import el2_pkg::*;
    input logic                             dbg_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
    input logic                             dma_bus_clk_en, // Clock ratio b/w cpu core clk & AHB slave interface
 
+   // ICCM/DCCM ECC status
+   output logic                            iccm_ecc_single_error,
+   output logic                            iccm_ecc_double_error,
+   output logic                            dccm_ecc_single_error,
+   output logic                            dccm_ecc_double_error,
+
  // all of these test inputs are brought to top-level; must be tied off based on usage by physical design (ie. icache or not, iccm or not, dccm or not)
 
    input                                   el2_ic_data_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,

design/ifu/el2_ifu.sv

@@ -149,7 +149,10 @@ import el2_pkg::*;
    input  logic [63:0]               iccm_rd_data,       // Data read from ICCM.
    input  logic [77:0]               iccm_rd_data_ecc,   // Data + ECC read from ICCM.
 
-   output logic                      ifu_iccm_rd_ecc_single_err, // This fetch has a single ICCM ecc  error.
+   // ICCM ECC status
+   output logic                      ifu_iccm_dma_rd_ecc_single_err, // This fetch has a single ICCM DMA ECC error.
+   output logic                      ifu_iccm_rd_ecc_single_err,     // This fetch has a single ICCM ECC error.
+   output logic                      ifu_iccm_rd_ecc_double_err,     // This fetch has a double ICCM ECC error.
 
 // Perf counter sigs
    output logic       ifu_pmu_ic_miss, // ic miss
@@ -216,7 +219,8 @@ import el2_pkg::*;
    logic [1:0]   ifu_fetch_val;  // valids on a 2B boundary, left justified [7] implies valid fetch
    logic [31:1]  ifu_fetch_pc;   // starting pc of fetch
 
-   logic iccm_rd_ecc_single_err, ic_error_start;
+   logic iccm_rd_ecc_single_err, iccm_dma_rd_ecc_single_err, ic_error_start;
+   assign ifu_iccm_dma_rd_ecc_single_err = iccm_dma_rd_ecc_single_err;
    assign ifu_iccm_rd_ecc_single_err = iccm_rd_ecc_single_err;
    assign ifu_ic_error_start = ic_error_start;
 
@@ -249,7 +253,9 @@ import el2_pkg::*;
    logic [31:0] ifu_fetch_data_f;
    logic ifc_fetch_req_f;
    logic ifc_fetch_req_f_raw;
+   logic iccm_dma_rd_ecc_double_err;
    logic [1:0] iccm_rd_ecc_double_err;  // This fetch has an iccm double error.
+   assign ifu_iccm_rd_ecc_double_err = |iccm_rd_ecc_double_err || |iccm_dma_rd_ecc_double_err;
 
    logic ifu_async_error_start;
 

design/ifu/el2_ifu_mem_ctl.sv

@@ -162,8 +162,10 @@ import el2_pkg::*;
    output logic                      ic_hit_f,               // Hit in Icache(if Icache access) or ICCM access( ICCM always has ic_hit_f)
    output logic [1:0]                ic_access_fault_f,      // Access fault (bus error or ICCM access in region but out of offset range).
    output logic [1:0]                ic_access_fault_type_f, // Access fault types
-   output logic                      iccm_rd_ecc_single_err, // This fetch has a single ICCM ecc  error.
-   output logic [1:0]                iccm_rd_ecc_double_err, // This fetch has a double ICCM ecc  error.
+   output logic                      iccm_rd_ecc_single_err, // This fetch has a single ICCM ECC error.
+   output logic [1:0]                iccm_rd_ecc_double_err, // This fetch has a double ICCM ECC error.
+   output logic                      iccm_dma_rd_ecc_single_err, // This fetch has a single ICCM DMA ECC error.
+   output logic                      iccm_dma_rd_ecc_double_err, // This fetch has a double ICCM DMA ECC error.
    output logic                      ic_error_start,         // This has any I$ errors ( data/tag/ecc/parity )
 
    output logic                      ifu_async_error_start,  // Or of the sb iccm, and all the icache errors sent to aligner to stop
@@ -1278,6 +1280,9 @@ ifc_dma_access_ok_prev,dma_iccm_req_f})
                                                  (~(ifc_dma_access_q_ok & dma_iccm_req) &  iccm_correct_ecc) ? {iccm_ecc_corr_index_ff[pt.ICCM_BITS-1:2],1'b0} : ifc_fetch_addr_bf[pt.ICCM_BITS-1:1] ;
 
 
+    assign iccm_dma_rd_ecc_single_err = iccm_dma_sb_error;
+    assign iccm_dma_rd_ecc_double_err = iccm_dma_rvalid && iccm_dma_ecc_error;
+
 
 
 /////////////////////////////////////////////////////////////////////////////////////

design/lsu/el2_lsu.sv

@@ -174,6 +174,10 @@ import el2_pkg::*;
    output logic [63:0]                     dccm_dma_rdata,      // lsu data for DMA dccm read
    output logic                            dccm_ready,          // lsu ready for DMA access
 
+   // DCCM ECC status
+   output logic                            lsu_dccm_rd_ecc_single_err,
+   output logic                            lsu_dccm_rd_ecc_double_err,
+
    input logic                             scan_mode,           // scan mode
    input logic                             clk,                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
    input logic                             active_clk,          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
@@ -211,6 +215,8 @@ import el2_pkg::*;
    logic        lsu_single_ecc_error_r;
    logic        lsu_double_ecc_error_r;
    logic        ld_single_ecc_error_r, ld_single_ecc_error_r_ff;
+   assign lsu_dccm_rd_ecc_single_err = lsu_single_ecc_error_r;
+   assign lsu_dccm_rd_ecc_double_err = lsu_double_ecc_error_r;
 
    logic [31:0] picm_mask_data_m;
 

testbench/tb_top.sv

@@ -795,6 +795,11 @@ veer_wrapper rvtop_wrapper (
     .dccm_bank_dout         (el2_mem_export.dccm_bank_dout),
     .dccm_bank_ecc          (el2_mem_export.dccm_bank_ecc),
 
+    .iccm_ecc_single_error  (),
+    .iccm_ecc_double_error  (),
+    .dccm_ecc_single_error  (),
+    .dccm_ecc_double_error  (),
+
 // remove mems DFT pins for opensource
     .ic_data_ext_in_pkt     ('0),
     .ic_tag_ext_in_pkt      ('0),

testbench/veer_wrapper.sv

@@ -326,6 +326,12 @@ module veer_wrapper
     input logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_DATA_WIDTH-1:0] dccm_bank_dout,
     input logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_FDATA_WIDTH-pt.DCCM_DATA_WIDTH-1:0] dccm_bank_ecc,
 
+    // ICCM/DCCM ECC status
+    output logic iccm_ecc_single_error,
+    output logic iccm_ecc_double_error,
+    output logic dccm_ecc_single_error,
+    output logic dccm_ecc_double_error,
+
     // external MPC halt/run interface
     input  logic mpc_debug_halt_req,  // Async halt request
     input  logic mpc_debug_run_req,   // Async run request