Skip to content

Commit

Permalink
Apply Verible on modified sources
Browse files Browse the repository at this point in the history
  • Loading branch information
@robertszczepanski
robertszczepanski committed Oct 4, 2023
1 parent 858d71a commit 4b7ee0a
Show file tree
Hide file tree
Showing 9 changed files with 472 additions and 457 deletions.
605 changes: 307 additions & 298 deletions design/dec/el2_dec.sv
View file

Large diffs are not rendered by default.

106 changes: 52 additions & 54 deletions design/el2_pmp.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,38 +15,37 @@
// limitations under the License.

module el2_pmp
import el2_pkg::*;
import el2_pkg::*;
#(
parameter PMP_CHANNELS = 3,
// Granularity of NAPOT access,
// 0 = No restriction, 1 = 8 byte, 2 = 16 byte, 3 = 32 byte, etc.
parameter PMP_GRANULARITY = 0, // TODO: Move to veer.config
`include "el2_param.vh"
)
(
input logic clk, // Top level clock
input logic rst_l, // Reset
input logic scan_mode, // Scan mode

input el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES],
input logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES],

input logic [31:0] pmp_chan_addr [PMP_CHANNELS],
input el2_pmp_type_pkt_t pmp_chan_type [PMP_CHANNELS],
output logic pmp_chan_err [PMP_CHANNELS]
);

logic [33:0] csr_pmp_addr_i [pt.PMP_ENTRIES];
logic [33:0] pmp_req_addr_i [PMP_CHANNELS];

logic [33:0] region_start_addr [pt.PMP_ENTRIES];
logic [33:PMP_GRANULARITY+2] region_addr_mask [pt.PMP_ENTRIES];
logic [PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_gt;
logic [PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_lt;
logic [PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_eq;
logic [PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_all;
logic [PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_basic_perm_check;
logic [PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_perm_check;
parameter PMP_CHANNELS = 3,
// Granularity of NAPOT access,
// 0 = No restriction, 1 = 8 byte, 2 = 16 byte, 3 = 32 byte, etc.
parameter PMP_GRANULARITY = 0, // TODO: Move to veer.config
`include "el2_param.vh"
) (
input logic clk, // Top level clock
input logic rst_l, // Reset
input logic scan_mode, // Scan mode

input el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES],
input logic [31:0] pmp_pmpaddr[pt.PMP_ENTRIES],

input logic [31:0] pmp_chan_addr[PMP_CHANNELS],
input el2_pmp_type_pkt_t pmp_chan_type[PMP_CHANNELS],
output logic pmp_chan_err [PMP_CHANNELS]
);

logic [ 33:0] csr_pmp_addr_i [pt.PMP_ENTRIES];
logic [ 33:0] pmp_req_addr_i [ PMP_CHANNELS];

logic [ 33:0] region_start_addr [pt.PMP_ENTRIES];
logic [33:PMP_GRANULARITY+2] region_addr_mask [pt.PMP_ENTRIES];
logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_gt;
logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_lt;
logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_eq;
logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_all;
logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_basic_perm_check;
logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_perm_check;

///////////////////////
// Functions for PMP //
Expand All @@ -62,23 +61,21 @@ import el2_pkg::*;

// A wrapper function in which it is decided which form of permission check function gets called
function automatic logic perm_check_wrapper(el2_pmp_cfg_pkt_t csr_pmp_cfg,
logic permission_check);
return orig_perm_check(csr_pmp_cfg.lock,
permission_check);
logic permission_check);
return orig_perm_check(csr_pmp_cfg.lock, permission_check);
endfunction

// Compute permissions checks that apply when MSECCFG.MML is unset. This is the original PMP
// behaviour before Smepmp was added.
function automatic logic orig_perm_check(logic pmp_cfg_lock,
logic permission_check);
return (~pmp_cfg_lock | permission_check);
// For M-mode, any region which matches with the L-bit clear, or with sufficient
// access permissions will be allowed
function automatic logic orig_perm_check(logic pmp_cfg_lock, logic permission_check);
return (~pmp_cfg_lock | permission_check);
// For M-mode, any region which matches with the L-bit clear, or with sufficient
// access permissions will be allowed
endfunction

// Access fault determination / prioritization
function automatic logic access_fault_check (logic [pt.PMP_ENTRIES-1:0] match_all,
logic [pt.PMP_ENTRIES-1:0] final_perm_check);
function automatic logic access_fault_check(logic [pt.PMP_ENTRIES-1:0] match_all,
logic [pt.PMP_ENTRIES-1:0] final_perm_check);


// When MSECCFG.MMWP is set default deny always, otherwise allow for M-mode, deny for other
Expand All @@ -102,11 +99,12 @@ import el2_pkg::*;
// ---------------

for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_addr_exp
assign csr_pmp_addr_i[r] = {pmp_pmpaddr[r], 2'b00}; // addr conv.: word @ 32-bit -> byte @ 34-bit
assign csr_pmp_addr_i[r] = {
pmp_pmpaddr[r], 2'b00
}; // addr conv.: word @ 32-bit -> byte @ 34-bit
// Start address for TOR matching
if (r == 0) begin : g_entry0
assign region_start_addr[r] = (pmp_pmpcfg[r].mode == TOR) ? 34'h000000000 :
csr_pmp_addr_i[r];
assign region_start_addr[r] = (pmp_pmpcfg[r].mode == TOR) ? 34'h000000000 : csr_pmp_addr_i[r];
end else begin : g_oth
assign region_start_addr[r] = (pmp_pmpcfg[r].mode == TOR) ? csr_pmp_addr_i[r-1] :
csr_pmp_addr_i[r];
Expand Down Expand Up @@ -134,7 +132,7 @@ import el2_pkg::*;
end

for (genvar c = 0; c < PMP_CHANNELS; c++) begin : g_access_check
assign pmp_req_addr_i[c] = {2'b00, pmp_chan_addr[c]}; // addr. widening: 32-bit -> 34-bit
assign pmp_req_addr_i[c] = {2'b00, pmp_chan_addr[c]}; // addr. widening: 32-bit -> 34-bit
for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_regions
// Comparators are sized according to granularity
assign region_match_eq[c][r] = (pmp_req_addr_i[c][33:PMP_GRANULARITY+2] &
Expand All @@ -149,14 +147,14 @@ import el2_pkg::*;
always_comb begin
region_match_all[c][r] = 1'b0;
unique case (pmp_pmpcfg[r].mode)
OFF: region_match_all[c][r] = 1'b0;
NA4: region_match_all[c][r] = region_match_eq[c][r];
NAPOT: region_match_all[c][r] = region_match_eq[c][r];
OFF: region_match_all[c][r] = 1'b0;
NA4: region_match_all[c][r] = region_match_eq[c][r];
NAPOT: region_match_all[c][r] = region_match_eq[c][r];
TOR: begin
region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) &
region_match_lt[c][r];
end
default: region_match_all[c][r] = 1'b0;
default: region_match_all[c][r] = 1'b0;
endcase
end

Expand All @@ -168,8 +166,9 @@ import el2_pkg::*;

// Check specific required permissions since the behaviour is different
// between Smepmp implementation and original PMP.
assign region_perm_check[c][r] = perm_check_wrapper(pmp_pmpcfg[r],
region_basic_perm_check[c][r]);
assign region_perm_check[c][r] = perm_check_wrapper(
pmp_pmpcfg[r], region_basic_perm_check[c][r]
);

// Address bits below PMP granularity (which starts at 4 byte) are deliberately unused.
logic unused_sigs;
Expand All @@ -179,8 +178,7 @@ import el2_pkg::*;

// Once the permission checks of the regions are done, decide if the access is
// denied by figuring out the matching region and its permission check.
assign pmp_chan_err[c] = access_fault_check(region_match_all[c],
region_perm_check[c]);
assign pmp_chan_err[c] = access_fault_check(region_match_all[c], region_perm_check[c]);
end

endmodule // el2_pmp
endmodule // el2_pmp
63 changes: 33 additions & 30 deletions design/el2_veer.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -726,21 +726,21 @@ import el2_pkg::*;
assign dccm_clk_override = dec_tlu_dccm_clk_override; // dccm memory
assign icm_clk_override = dec_tlu_icm_clk_override; // icache/iccm memory

// PMP Signals
el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES];
logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES];
logic [31:0] pmp_chan_addr [3];
el2_pmp_type_pkt_t pmp_chan_type [3];
logic pmp_chan_err [3];

logic [31:1] ifu_pmp_addr;
logic ifu_pmp_error;
logic [31:0] lsu_pmp_addr_start;
logic lsu_pmp_error_start;
logic [31:0] lsu_pmp_addr_end;
logic lsu_pmp_error_end;
logic lsu_pmp_we;
logic lsu_pmp_re;
// PMP Signals
el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES];
logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES];
logic [31:0] pmp_chan_addr [3];
el2_pmp_type_pkt_t pmp_chan_type [3];
logic pmp_chan_err [3];

logic [31:1] ifu_pmp_addr;
logic ifu_pmp_error;
logic [31:0] lsu_pmp_addr_start;
logic lsu_pmp_error_start;
logic [31:0] lsu_pmp_addr_end;
logic lsu_pmp_error_end;
logic lsu_pmp_we;
logic lsu_pmp_re;

// -----------------------DEBUG START -------------------------------

Expand Down Expand Up @@ -970,21 +970,24 @@ import el2_pkg::*;
.*
);

assign pmp_chan_addr[0] = {ifu_pmp_addr, 1'b0};
assign pmp_chan_type[0] = EXEC;
assign ifu_pmp_error = pmp_chan_err[0];
assign pmp_chan_addr[1] = lsu_pmp_addr_start;
assign pmp_chan_type[1] = lsu_pmp_we ? WRITE : (lsu_pmp_re ? READ : NONE);
assign lsu_pmp_error_start = pmp_chan_err[1];
assign pmp_chan_addr[2] = lsu_pmp_addr_end;
assign pmp_chan_type[2] = lsu_pmp_we ? WRITE : (lsu_pmp_re ? READ : NONE);
assign lsu_pmp_error_end = pmp_chan_err[2];

el2_pmp #(.PMP_CHANNELS(3), .pt(pt)) pmp (
.clk(active_l2clk),
.rst_l(core_rst_l),
.*
);
assign pmp_chan_addr[0] = {ifu_pmp_addr, 1'b0};
assign pmp_chan_type[0] = EXEC;
assign ifu_pmp_error = pmp_chan_err[0];
assign pmp_chan_addr[1] = lsu_pmp_addr_start;
assign pmp_chan_type[1] = lsu_pmp_we ? WRITE : (lsu_pmp_re ? READ : NONE);
assign lsu_pmp_error_start = pmp_chan_err[1];
assign pmp_chan_addr[2] = lsu_pmp_addr_end;
assign pmp_chan_type[2] = lsu_pmp_we ? WRITE : (lsu_pmp_re ? READ : NONE);
assign lsu_pmp_error_end = pmp_chan_err[2];

el2_pmp #(
.PMP_CHANNELS(3),
.pt(pt)
) pmp (
.clk (active_l2clk),
.rst_l(core_rst_l),
.*
);

if (pt.BUILD_AHB_LITE == 1) begin: Gen_AXI_To_AHB

Check warning on line 992 in design/el2_veer.sv

View workflow job for this annotation

GitHub Actions / format-review 

[verible-verilog-format] reported by reviewdog 🐶


Raw Output:
design/el2_veer.sv:992:-   if (pt.BUILD_AHB_LITE == 1) begin: Gen_AXI_To_AHB
design/el2_veer.sv:993:-
design/el2_veer.sv:994:-      // AXI4 -> AHB Gasket for LSU
design/el2_veer.sv:995:-      axi4_to_ahb #(.pt(pt),
design/el2_veer.sv:996:-                    .TAG(pt.LSU_BUS_TAG)) lsu_axi4_to_ahb (
design/el2_veer.sv:997:-
design/el2_veer.sv:998:-         .clk(free_l2clk),
design/el2_veer.sv:999:-         .free_clk(free_clk),
design/el2_veer.sv:1000:-         .rst_l(core_rst_l),
design/el2_veer.sv:1001:-         .clk_override(dec_tlu_bus_clk_override),
design/el2_veer.sv:1002:-         .bus_clk_en(lsu_bus_clk_en),
design/el2_veer.sv:1003:-         .dec_tlu_force_halt(dec_tlu_force_halt),
design/el2_veer.sv:1004:-
design/el2_veer.sv:1005:-         // AXI Write Channels
design/el2_veer.sv:1006:-         .axi_awvalid(lsu_axi_awvalid),
design/el2_veer.sv:1007:-         .axi_awready(lsu_axi_awready_ahb),
design/el2_veer.sv:1008:-         .axi_awid(lsu_axi_awid[pt.LSU_BUS_TAG-1:0]),
design/el2_veer.sv:1009:-         .axi_awaddr(lsu_axi_awaddr[31:0]),
design/el2_veer.sv:1010:-         .axi_awsize(lsu_axi_awsize[2:0]),
design/el2_veer.sv:1011:-         .axi_awprot(lsu_axi_awprot[2:0]),
design/el2_veer.sv:1012:-
design/el2_veer.sv:1013:-         .axi_wvalid(lsu_axi_wvalid),
design/el2_veer.sv:1014:-         .axi_wready(lsu_axi_wready_ahb),
design/el2_veer.sv:1015:-         .axi_wdata(lsu_axi_wdata[63:0]),
design/el2_veer.sv:1016:-         .axi_wstrb(lsu_axi_wstrb[7:0]),
design/el2_veer.sv:1017:-         .axi_wlast(lsu_axi_wlast),
design/el2_veer.sv:1018:-
design/el2_veer.sv:1019:-         .axi_bvalid(lsu_axi_bvalid_ahb),
design/el2_veer.sv:1020:-         .axi_bready(lsu_axi_bready),
design/el2_veer.sv:1021:-         .axi_bresp(lsu_axi_bresp_ahb[1:0]),
design/el2_veer.sv:1022:-         .axi_bid(lsu_axi_bid_ahb[pt.LSU_BUS_TAG-1:0]),
design/el2_veer.sv:1023:-
design/el2_veer.sv:1024:-         // AXI Read Channels
design/el2_veer.sv:1025:-         .axi_arvalid(lsu_axi_arvalid),
design/el2_veer.sv:1026:-         .axi_arready(lsu_axi_arready_ahb),
design/el2_veer.sv:1027:-         .axi_arid(lsu_axi_arid[pt.LSU_BUS_TAG-1:0]),
design/el2_veer.sv:1028:-         .axi_araddr(lsu_axi_araddr[31:0]),
design/el2_veer.sv:1029:-         .axi_arsize(lsu_axi_arsize[2:0]),
design/el2_veer.sv:1030:-         .axi_arprot(lsu_axi_arprot[2:0]),
design/el2_veer.sv:1031:-
design/el2_veer.sv:1032:-         .axi_rvalid(lsu_axi_rvalid_ahb),
design/el2_veer.sv:1033:-         .axi_rready(lsu_axi_rready),
design/el2_veer.sv:1034:-         .axi_rid(lsu_axi_rid_ahb[pt.LSU_BUS_TAG-1:0]),
design/el2_veer.sv:1035:-         .axi_rdata(lsu_axi_rdata_ahb[63:0]),
design/el2_veer.sv:1036:-         .axi_rresp(lsu_axi_rresp_ahb[1:0]),
design/el2_veer.sv:1037:-         .axi_rlast(lsu_axi_rlast_ahb),
design/el2_veer.sv:1038:-
design/el2_veer.sv:1039:-         // AHB-LITE signals
design/el2_veer.sv:1040:-         .ahb_haddr(lsu_haddr[31:0]),
design/el2_veer.sv:1041:-         .ahb_hburst(lsu_hburst),
design/el2_veer.sv:1042:-         .ahb_hmastlock(lsu_hmastlock),
design/el2_veer.sv:1043:-         .ahb_hprot(lsu_hprot[3:0]),
design/el2_veer.sv:1044:-         .ahb_hsize(lsu_hsize[2:0]),
design/el2_veer.sv:1045:-         .ahb_htrans(lsu_htrans[1:0]),
design/el2_veer.sv:1046:-         .ahb_hwrite(lsu_hwrite),
design/el2_veer.sv:1047:-         .ahb_hwdata(lsu_hwdata[63:0]),
design/el2_veer.sv:1048:-
design/el2_veer.sv:1049:-         .ahb_hrdata(lsu_hrdata[63:0]),
design/el2_veer.sv:1050:-         .ahb_hready(lsu_hready),
design/el2_veer.sv:1051:-         .ahb_hresp(lsu_hresp),
design/el2_veer.sv:1052:-
design/el2_veer.sv:1053:-         .*
design/el2_veer.sv:1054:-      );
design/el2_veer.sv:1055:-
design/el2_veer.sv:1056:-      axi4_to_ahb #(.pt(pt),
design/el2_veer.sv:1057:-                    .TAG(pt.IFU_BUS_TAG)) ifu_axi4_to_ahb (
design/el2_veer.sv:1058:-         .clk(free_l2clk),
design/el2_veer.sv:1059:-         .free_clk(free_clk),
design/el2_veer.sv:1060:-         .rst_l(core_rst_l),
design/el2_veer.sv:1061:-

Expand Down
6 changes: 3 additions & 3 deletions design/ifu/el2_ifu.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -193,8 +193,8 @@ import el2_pkg::*;

output logic [15:0] ifu_i0_cinst,

output logic [31:1] ifu_pmp_addr,
input logic ifu_pmp_error,
output logic [31:1] ifu_pmp_addr,
input logic ifu_pmp_error,

/// Icache debug

Check warning on line 199 in design/ifu/el2_ifu.sv

View workflow job for this annotation

GitHub Actions / format-review 

[verible-verilog-format] reported by reviewdog 🐶


Raw Output:
design/ifu/el2_ifu.sv:199:-/// Icache debug
design/ifu/el2_ifu.sv:200:-   input  el2_cache_debug_pkt_t        dec_tlu_ic_diag_pkt ,
design/ifu/el2_ifu.sv:201:-   output logic                    ifu_ic_debug_rd_data_valid,
design/ifu/el2_ifu.sv:202:-   output logic                                iccm_buf_correct_ecc,
design/ifu/el2_ifu.sv:203:-   output logic                                iccm_correction_state,
design/ifu/el2_ifu.sv:198:+    /// Icache debug
design/ifu/el2_ifu.sv:199:+    input  el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt,
design/ifu/el2_ifu.sv:200:+    output logic                 ifu_ic_debug_rd_data_valid,
design/ifu/el2_ifu.sv:201:+    output logic                 iccm_buf_correct_ecc,
design/ifu/el2_ifu.sv:202:+    output logic                 iccm_correction_state,
input el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt ,
Expand All @@ -211,7 +211,7 @@ import el2_pkg::*;
logic ifu_fb_consume1, ifu_fb_consume2;
logic [31:1] ifc_fetch_addr_f;
logic [31:1] ifc_fetch_addr_bf;
assign ifu_pmp_addr = ifc_fetch_addr_bf;
assign ifu_pmp_addr = ifc_fetch_addr_bf;

logic [1:0] ifu_fetch_val; // valids on a 2B boundary, left justified [7] implies valid fetch

Check warning on line 216 in design/ifu/el2_ifu.sv

View workflow job for this annotation

GitHub Actions / format-review 

[verible-verilog-format] reported by reviewdog 🐶


Raw Output:
design/ifu/el2_ifu.sv:216:-   logic [1:0]   ifu_fetch_val;  // valids on a 2B boundary, left justified [7] implies valid fetch
design/ifu/el2_ifu.sv:217:-   logic [31:1]  ifu_fetch_pc;   // starting pc of fetch
design/ifu/el2_ifu.sv:218:-
design/ifu/el2_ifu.sv:219:-   logic iccm_rd_ecc_single_err, ic_error_start;
design/ifu/el2_ifu.sv:220:-   assign ifu_iccm_rd_ecc_single_err = iccm_rd_ecc_single_err;
design/ifu/el2_ifu.sv:221:-   assign ifu_ic_error_start = ic_error_start;
design/ifu/el2_ifu.sv:222:-
design/ifu/el2_ifu.sv:223:-
design/ifu/el2_ifu.sv:224:-   logic        ic_write_stall;
design/ifu/el2_ifu.sv:225:-   logic        ic_dma_active;
design/ifu/el2_ifu.sv:226:-   logic        ifc_dma_access_ok;
design/ifu/el2_ifu.sv:227:-   logic [1:0]  ic_access_fault_f;
design/ifu/el2_ifu.sv:228:-   logic [1:0]  ic_access_fault_type_f;
design/ifu/el2_ifu.sv:229:-   logic        ifu_ic_mb_empty;
design/ifu/el2_ifu.sv:230:-
design/ifu/el2_ifu.sv:231:-   logic ic_hit_f;
design/ifu/el2_ifu.sv:232:-
design/ifu/el2_ifu.sv:233:-   logic [1:0] ifu_bp_way_f; // way indication; right justified
design/ifu/el2_ifu.sv:234:-   logic       ifu_bp_hit_taken_f; // kill next fetch; taken target found
design/ifu/el2_ifu.sv:235:-   logic [31:1] ifu_bp_btb_target_f; //  predicted target PC
design/ifu/el2_ifu.sv:236:-   logic        ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified
design/ifu/el2_ifu.sv:237:-   logic [1:0]  ifu_bp_hist1_f; // history counters for all 4 potential branches; right justified
design/ifu/el2_ifu.sv:238:-   logic [1:0]  ifu_bp_hist0_f; // history counters for all 4 potential branches; right justified
design/ifu/el2_ifu.sv:239:-   logic [11:0] ifu_bp_poffset_f; // predicted target
design/ifu/el2_ifu.sv:240:-   logic [1:0]  ifu_bp_ret_f; // predicted ret ; right justified
design/ifu/el2_ifu.sv:241:-   logic [1:0]  ifu_bp_pc4_f; // pc4 indication; right justified
design/ifu/el2_ifu.sv:242:-   logic [1:0]  ifu_bp_valid_f; // branch valid, right justified
design/ifu/el2_ifu.sv:243:-   logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f;
design/ifu/el2_ifu.sv:244:-   logic [1:0] [$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f;
design/ifu/el2_ifu.sv:245:-
design/ifu/el2_ifu.sv:246:-
design/ifu/el2_ifu.sv:247:-   logic [1:0]   ic_fetch_val_f;
design/ifu/el2_ifu.sv:248:-   logic [31:0] ic_data_f;
design/ifu/el2_ifu.sv:249:-   logic [31:0] ifu_fetch_data_f;
design/ifu/el2_ifu.sv:250:-   logic ifc_fetch_req_f;
design/ifu/el2_ifu.sv:251:-   logic ifc_fetch_req_f_raw;
design/ifu/el2_ifu.sv:252:-   logic [1:0] iccm_rd_ecc_double_err;  // This fetch has an iccm double error.
design/ifu/el2_ifu.sv:253:-
design/ifu/el2_ifu.sv:254:-   logic ifu_async_error_start;
design/ifu/el2_ifu.sv:255:-
design/ifu/el2_ifu.sv:256:-
design/ifu/el2_ifu.sv:257:-   assign ifu_fetch_data_f[31:0] = ic_data_f[31:0];
design/ifu/el2_ifu.sv:258:-   assign ifu_fetch_val[1:0] = ic_fetch_val_f[1:0];
design/ifu/el2_ifu.sv:259:-   assign ifu_fetch_pc[31:1] = ifc_fetch_addr_f[31:1];
design/ifu/el2_ifu.sv:260:-
design/ifu/el2_ifu.sv:261:- logic                       ifc_fetch_uncacheable_bf;      // The fetch request is uncacheable space. BF stage
design/ifu/el2_ifu.sv:262:- logic                       ifc_fetch_req_bf;              // Fetch request. Comes with the address.  BF stage
design/ifu/el2_ifu.sv:263:- logic                       ifc_fetch_req_bf_raw;          // Fetch request without some qualifications. Used for clock-gating. BF stage
design/ifu/el2_ifu.sv:264:- logic                       ifc_iccm_access_bf;            // This request is to the ICCM. Do not generate misses to the bus.
design/ifu/el2_ifu.sv:265:- logic                       ifc_region_acc_fault_bf;       // Access fault. in ICCM region but offset is outside defined ICCM.
design/ifu/el2_ifu.sv:266:-
design/ifu/el2_ifu.sv:267:-   // fetch control
design/ifu/el2_ifu.sv:268:-   el2_ifu_ifc_ctl #(.pt(pt)) ifc (.*
design/ifu/el2_ifu.sv:269:-                    );
design/ifu/el2_ifu.sv:270:-
design/ifu/el
logic [31:1] ifu_fetch_pc; // starting pc of fetch
Expand Down
48 changes: 24 additions & 24 deletions design/include/el2_def.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -406,30 +406,30 @@ typedef struct packed {
} el2_cache_debug_pkt_t;


typedef enum logic [2:0] {
NONE = 3'b000,
READ = 3'b001,
WRITE = 3'b010,
EXEC = 3'b100
} el2_pmp_type_pkt_t;


typedef enum logic [1:0] {
OFF = 2'b00,
TOR = 2'b01,
NA4 = 2'b10,
NAPOT = 2'b11
} el2_pmp_mode_pkt_t;


typedef struct packed {
logic lock;
logic [1:0] reserved;
el2_pmp_mode_pkt_t mode;
logic execute;
logic write;
logic read;
} el2_pmp_cfg_pkt_t;
typedef enum logic [2:0] {
NONE = 3'b000,
READ = 3'b001,
WRITE = 3'b010,
EXEC = 3'b100
} el2_pmp_type_pkt_t;


typedef enum logic [1:0] {
OFF = 2'b00,
TOR = 2'b01,
NA4 = 2'b10,
NAPOT = 2'b11
} el2_pmp_mode_pkt_t;


typedef struct packed {
logic lock;
logic [1:0] reserved;
el2_pmp_mode_pkt_t mode;
logic execute;
logic write;
logic read;
} el2_pmp_cfg_pkt_t;
//`endif

endpackage // el2_pkg
26 changes: 13 additions & 13 deletions design/lsu/el2_lsu.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -177,14 +177,14 @@ import el2_pkg::*;
input logic scan_mode, // scan mode
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
input logic rst_l, // reset, active low
input logic rst_l, // reset, active low

output logic [31:0] lsu_pmp_addr_start,
output logic [31:0] lsu_pmp_addr_end,
input logic lsu_pmp_error_start,
input logic lsu_pmp_error_end,
output logic lsu_pmp_we,
output logic lsu_pmp_re
output logic [31:0] lsu_pmp_addr_start,
output logic [31:0] lsu_pmp_addr_end,
input logic lsu_pmp_error_start,
input logic lsu_pmp_error_end,
output logic lsu_pmp_we,
output logic lsu_pmp_re

);

Expand Down Expand Up @@ -216,13 +216,13 @@ import el2_pkg::*;

logic [31:0] lsu_addr_d, lsu_addr_m, lsu_addr_r;
logic [31:0] end_addr_d, end_addr_m, end_addr_r;
assign lsu_pmp_addr_start = lsu_addr_d;
assign lsu_pmp_addr_end = end_addr_d;
assign lsu_pmp_addr_start = lsu_addr_d;
assign lsu_pmp_addr_end = end_addr_d;

el2_lsu_pkt_t lsu_pkt_d, lsu_pkt_m, lsu_pkt_r;
logic lsu_i0_valid_d, lsu_i0_valid_m, lsu_i0_valid_r;
assign lsu_pmp_we = lsu_pkt_d.store & lsu_pkt_d.valid;
assign lsu_pmp_re = lsu_pkt_d.load & lsu_pkt_d.valid;
assign lsu_pmp_we = lsu_pkt_d.store & lsu_pkt_d.valid;
assign lsu_pmp_re = lsu_pkt_d.load & lsu_pkt_d.valid;

// Store Buffer signals
logic store_stbuf_reqvld_r;
Expand Down Expand Up @@ -317,8 +317,8 @@ import el2_pkg::*;
// Store buffer now have only non-dma dccm stores
// stbuf_empty not needed since it has only dccm stores
assign lsu_idle_any = ~((lsu_pkt_m.valid & ~lsu_pkt_m.dma) |
(lsu_pkt_r.valid & ~lsu_pkt_r.dma)) &
lsu_bus_buffer_empty_any;
(lsu_pkt_r.valid & ~lsu_pkt_r.dma)) &
lsu_bus_buffer_empty_any;

assign lsu_active = (lsu_pkt_m.valid | lsu_pkt_r.valid | ld_single_ecc_error_r_ff) | ~lsu_bus_buffer_empty_any; // This includes DMA. Used for gating top clock

Expand Down
Loading

0 comments on commit 4b7ee0a

Please sign in to comment.