Refactor AHB vs. AXI4 PyUVM monitor class

Internal-tag: [#51803]
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

verification/block/lib_ahb_to_axi4/testbench.py

@@ -138,7 +138,7 @@ async def write(self, addr, data):
         # Address phase
         await RisingEdge(self.ahb_hclk)
         self.ahb_hsel.value = 1
-        self.ahb_hprot.value = 1 # Indicates a data transfer
+        self.ahb_hprot.value = 1  # Indicates a data transfer
         self.ahb_hsize.value = self.hsize[lnt]
         self.ahb_haddr.value = addr
         self.ahb_hwrite.value = 1
@@ -491,13 +491,7 @@ def connect_phase(self):
 
     def check_phase(self):
         # Check transactions
-        while self.ahb_port.can_get() or self.axi_port.can_get():
-            # A transaction is missing
-            if not self.ahb_port.can_get() or not self.axi_port.can_get():
-                self.logger.error("A transaction is missing on one of the buses")
-                self.passed = False
-                break
-
+        while self.ahb_port.can_get() and self.axi_port.can_get():
             self.passed = True
 
             # Get items
@@ -523,6 +517,12 @@ def check_phase(self):
             else:
                 self.logger.debug(msg)
 
+        # Indicate an error if there is any leftover transaction in any of the
+        # queues.
+        if self.ahb_port.can_get() or self.axi_port.can_get():
+            self.logger.error("Spurious transaction(s) on one of the buses")
+            self.passed = False
+
     def final_phase(self):
         if not self.passed:
             self.logger.critical("{} reports a failure".format(type(self)))