Skip to content

Commit

Permalink
Added riscv-dv CI test exclusion
Browse files Browse the repository at this point in the history
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
  • Loading branch information
mkurc-ant committed Sep 28, 2023
1 parent 841f626 commit a159639
Show file tree
Hide file tree
Showing 2 changed files with 13 additions and 0 deletions.
11 changes: 11 additions & 0 deletions .github/scripts/riscv_dv_parse_testlist.py
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
import sys
import os
from json import dumps
from yaml import load, Loader
from typing import Generator
Expand All @@ -24,6 +25,16 @@ def parse_yaml(path: str) -> Generator[str, None, None]:
else:
testlist = parse_yaml(RISCV_DV_HOME + 'yaml/base_testlist.yaml')
testlist = list(testlist)

# remove, will cause incomplete sim, need customized RTL
testlist.remove("riscv_csr_test")

# remove excluded tests
excluded = os.environ.get("EXCLUDE_TESTS", None)
if excluded is not None:
excluded = [s.strip() for s in excluded.split(",")]
for test in excluded:
if test in testlist:
testlist.remove(test)

print(dumps(testlist))
2 changes: 2 additions & 0 deletions .github/workflows/test-riscv-dv.yml
Original file line number Diff line number Diff line change
Expand Up @@ -107,6 +107,8 @@ jobs:
generate-config:
name: Generate configs
runs-on: ubuntu-latest
env:
EXCLUDE_TESTS: "riscv_illegal_instr_test,riscv_unaligned_load_store_test"
outputs:
test-types: ${{ steps.test-types.outputs.tests }}
test-include-generate: ${{ steps.test-types.outputs.include-generate }}
Expand Down

0 comments on commit a159639

Please sign in to comment.