Fix AXI4 to AHB converter issues #141
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| @@ -345,8 +354,8 @@ import el2_pkg::*; | |||
| end | |||
| DATA_WR: begin | |||
| buf_state_en = (cmd_doneQ & ahb_hready_q) | ahb_hresp_q; | |||
| master_ready = buf_state_en & ~ahb_hresp_q & slave_ready; // Ready to accept new command if current command done and no error | |||
| buf_nxtstate = (ahb_hresp_q | ~slave_ready) ? DONE : | |||
| master_ready = buf_state_en & ~ahb_hresp_q & axi_bready; // Ready to accept new command if current command done and no error | |||
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| @@ -403,7 +422,7 @@ import el2_pkg::*; | |||
| assign slave_valid = slave_valid_pre;// & (~slvbuf_posted_write | slvbuf_error); | |||
| assign slave_opc[3:2] = slvbuf_write ? 2'b11 : 2'b00; | |||
| assign slave_opc[1:0] = {2{slvbuf_error}} & 2'b10; | |||
| assign slave_rdata[63:0] = slvbuf_error ? {2{last_bus_addr[31:0]}} : ((buf_state == DONE) ? buf_data[63:0] : ahb_hrdata_q[63:0]); | |||
| assign slave_rdata[63:0] = slvbuf_error ? {2{last_bus_addr[31:0]}} : ((buf_state == DONE_RD) ? buf_data[63:0] : ahb_hrdata_q[63:0]); | |||
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Internal-Tag: [#49716] Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Internal-Tag: [#49716] Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Internal-Tag: [#49716] Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
…eter. Internal-Tag: [#49716] Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Internal-Tag: [#49716] Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Internal-Tag: [#49716] Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Links to coverage and verification reports for this PR (#141) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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LGTM |
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This PR fixes incorrect operation of
axi4_to_ahbconverter module wherervalidandbvaliddepend onrreadyandbreadyrespectively which is forbidden by the spec.Microarchitectural tests are updated to exercise correct AXI channel handshaking. A VeeR configuration with AHB bus where the
axi4_to_ahbmodule is used is added to CI regression tests.