Improve PMP microarchitectural tests #143
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LGTM |
Internal-Tag: [#52259] Signed-off-by: Robert Szczepanski <rszczepanski@antmicro.com>
Internal-Tag: [#52259] Signed-off-by: Robert Szczepanski <rszczepanski@antmicro.com>
Internal-Tag: [#52259] Signed-off-by: Robert Szczepanski <rszczepanski@antmicro.com>
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Links to coverage and verification reports for this PR (#143) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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This PR introduces improvements for microarchitetural tests:
verification/block.