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Add JTAG type as a configurable parameter #152

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Add JTAG type as a configurable parameter #152

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e8bbd53
Add JTAG type as a configurable parameter
robertszczepanski Dec 13, 2023
9bac601
Set default JTAG ID to 0
robertszczepanski Dec 13, 2023
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19 changes: 16 additions & 3 deletions configs/veer.config
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Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ my @argv_orig = @ARGV;
my $defines_case = "U";

# Include these macros in verilog (pattern matched)
my @verilog_vars = qw (xlen config_key reset_vec tec_rv_icg numiregs nmi_vec target protection.* testbench.* dccm.* retstack core.* iccm.* btb.* bht.* icache.* pic.* regwidth memmap bus.* tech_specific_.* user_.*);
my @verilog_vars = qw (xlen config_key reset_vec tec_rv_icg numiregs nmi_vec target protection.* testbench.* dccm.* retstack core.* iccm.* btb.* bht.* icache.* pic.* regwidth memmap bus.* tech_specific_.* user_.* jtag_type jtag_no_idcode);

# Include these macros in assembly (pattern matched)
my @asm_vars = qw (xlen reset_vec nmi_vec target dccm.* iccm.* pic.* memmap testbench.* protection.* core.*);
Expand All @@ -48,7 +48,7 @@ my @dvars = qw(retstack btb bht core dccm iccm icache pic protection memmap bus)
# Prefix all macros with
my $prefix = "RV_";
# No prefix if keyword has
my $no_prefix = 'RV|TOP|tec_rv_icg|regwidth|clock_period|^datawidth|verilator|SDVT_AHB|tech_specific_.*|user_.*';
my $no_prefix = 'RV|TOP|tec_rv_icg|regwidth|clock_period|^datawidth|verilator|SDVT_AHB|tech_specific_.*|user_.*|jtag_type';

my $vlog_use__wh = 1;

Expand Down Expand Up @@ -201,6 +201,8 @@ Parameters that can be set by the end user:
Don't add ICCM preload code in generated link.ld
-set=pmp_entries = {0, 16, 64 }
number of PMP entries
-set=jtag_type = {cltapc, emtapc}
Type of JTAG TAP controller, can be either a centralized TAP or an embedded TAP


Additionally the following may be set for bus masters and slaves using the -set=var=value option:
Expand Down Expand Up @@ -309,6 +311,7 @@ my $div_bit=4; # number of bits to process each cycle for div
my $div_new=1; # old or new div algorithm

my $fpga_optimize = 1;
my $jtag_type = "cltapc";

# Default bitmanip options
my $bitmanip_zba = 1;
Expand Down Expand Up @@ -358,6 +361,7 @@ GetOptions(
"unset=s@" => \@unsets,
"fpga_optimize=s" => \$fpga_optimize,
"text_in_iccm" => \$text_in_iccm,
"jtag_type=s" => \$jtag_type,
) || die("$helpusage");

if ($help) {
Expand Down Expand Up @@ -851,6 +855,7 @@ our %config = (#{{{
"target" => $target, # Flow Infrastructure
"config_key" => "derived",
"tec_rv_icg" => "clockhdr",
"jtag_type" => $jtag_type,

"retstack" => {
"ret_stack_size" => "$ret_stack_size", # Design Parm, Overridable
Expand Down Expand Up @@ -1325,6 +1330,15 @@ gen_define("","", \%config,"",[]);

# perform final checks
my $c;

$c=$config{jtag_type};
if ($c eq "emtapc") {
$config{jtag_no_idcode}=1;
}
elsif (!($c eq "cltapc")) {
die("$helpusage\n\nFAIL: jtag_type == $c ILLEGAL !!!\n\n");
}

$c=$config{retstack}{ret_stack_size}; if (!($c >=2 && $c <=8)) { die("$helpusage\n\nFAIL: ret_stack_size == $c; ILLEGAL !!!\n\n"); }
$c=$config{btb}{btb_size}; if (!($c==8||$c==16||$c==32||$c==64||$c==128||$c==256||$c==512)) { die("$helpusage\n\nFAIL: btb_size == $c; ILLEGAL !!!\n\n"); }
$c=$config{btb}{btb_size}; if (($c==64||$c==128||$c==256||$c==512) && $config{btb}{btb_fullya}) { die("$helpusage\n\nFAIL: btb_size == $c; btb_fullya=1 ILLEGAL !!!\n\n"); }
Expand Down Expand Up @@ -1358,7 +1372,6 @@ $c=$config{core}{lsu_stbuf_depth}; if (!($c==2 || $c==4 || $c==8))
$c=$config{core}{dma_buf_depth}; if (!($c==2 || $c==4 || $c==5)) { die("$helpusage\n\nFAIL: dma_buf_depth == $c ILLEGAL !!!\n\n"); }
$c=$config{core}{lsu_num_nbload}; if (!($c==2 || $c==4 || $c==8)) { die("$helpusage\n\nFAIL: lsu_num_nbload == $c ILLEGAL !!!\n\n"); }


# force div_bit to be 1 for old div algorithm
if ($config{core}{div_new}==0 && $config{core}{div_bit}!=1) {
die("$helpusage\n\nFAIL: div_new=0 requires div_bit=1 ILLEGAL !!!\n\n");
Expand Down
25 changes: 15 additions & 10 deletions design/dmi/rvjtag_tap.v
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Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: Apache-2.0
// Copyright 2019 Western Digital Corporation or it's affiliates.
// Copyright (c) 2023 Antmicro <www.antmicro.com>
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
Expand Down Expand Up @@ -37,12 +38,8 @@ output reg dmi_hard_reset,

input [2:0] idle,
input [1:0] dmi_stat,
/*
-- revisionCode : 4'h0;
-- manufacturersIdCode : 11'h45;
-- deviceIdCode : 16'h0001;
-- order MSB .. LSB -> [4 bit version or revision] [16 bit part number] [11 bit manufacturer id] [value of 1'b1 in LSB]
*/

// JTAG ID order MSB .. LSB -> [4 bit version or revision] [16 bit part number] [11 bit manufacturer id] [value of 1'b1 in LSB]
input [31:1] jtag_id,
input [3:0] version
);
Expand All @@ -67,9 +64,12 @@ wire pause_ir ;
wire update_ir ;
wire capture_ir;
wire[1:0] dr_en;
wire devid_sel;
wire [5:0] abits;

`ifndef RV_JTAG_NO_IDCODE
wire devid_sel;
`endif

assign abits = AWIDTH[5:0];


Expand Down Expand Up @@ -142,8 +142,9 @@ always @ (negedge tck or negedge trst) begin
end
end


`ifndef RV_JTAG_NO_IDCODE
assign devid_sel = ir == 5'b00001;
`endif
assign dr_en[0] = ir == 5'b10000;
assign dr_en[1] = ir == 5'b10001;

Expand All @@ -167,8 +168,10 @@ always_comb begin
case(1)
dr_en[1]: nsr = {tdi, sr[USER_DR_LENGTH-1:1]};

dr_en[0],
devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}},tdi, sr[31:1]};
`ifndef RV_JTAG_NO_IDCODE
devid_sel,
`endif
dr_en[0]: nsr = {{USER_DR_LENGTH-32{1'b0}},tdi, sr[31:1]};
default: nsr = {{USER_DR_LENGTH-1{1'b0}},tdi}; // bypass
endcase
end
Expand All @@ -177,7 +180,9 @@ always_comb begin
case(1)
dr_en[0]: nsr = {{USER_DR_LENGTH-15{1'b0}}, idle, dmi_stat, abits, version};
dr_en[1]: nsr = {{AWIDTH{1'b0}}, rd_data, rd_status};
`ifndef RV_JTAG_NO_IDCODE
devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}}, jtag_id, 1'b1};
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`endif
endcase
end
shift_ir: nsr = {{USER_DR_LENGTH-5{1'b0}},tdi, sr[4:1]};
Expand Down
4 changes: 1 addition & 3 deletions testbench/tb_top.sv
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Expand Up @@ -442,9 +442,7 @@ module tb_top (
abi_reg[30] = "t5";
abi_reg[31] = "t6";
// tie offs
jtag_id[31:28] = 4'b1;
jtag_id[27:12] = '0;
jtag_id[11:1] = 11'h45;
jtag_id[31:1] = 31'h0;
reset_vector = `RV_RESET_VEC;
nmi_vector = 32'hee000000;
nmi_int = 0;
Expand Down