Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Move perr_dat_ff closer to ICACHE_ENABLE-gated logic #153

Merged
merged 1 commit into from
Mar 27, 2024
Merged

Move perr_dat_ff closer to ICACHE_ENABLE-gated logic #153

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Jump to
Jump to file
Failed to load files.
Diff view
Diff view
102 changes: 54 additions & 48 deletions design/ifu/el2_ifu_mem_ctl.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@
module el2_ifu_mem_ctl
import el2_pkg::*;
#(
`include "el2_param.vh"

Check warning on line 27 in design/ifu/el2_ifu_mem_ctl.sv

View workflow job for this annotation

GitHub Actions / format-review 

[verible-verilog-format] reported by reviewdog 🐶


Raw Output:
design/ifu/el2_ifu_mem_ctl.sv:27:-`include "el2_param.vh"
design/ifu/el2_ifu_mem_ctl.sv:28:- )
design/ifu/el2_ifu_mem_ctl.sv:29:-  (
design/ifu/el2_ifu_mem_ctl.sv:30:-   input logic clk,                                                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
design/ifu/el2_ifu_mem_ctl.sv:31:-   input logic active_clk,                                          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
design/ifu/el2_ifu_mem_ctl.sv:32:-   input logic free_l2clk,                                          // Clock always.                  Through one clock header.  For flops with    second header built in.
design/ifu/el2_ifu_mem_ctl.sv:33:-   input logic rst_l,                                               // reset, active low
design/ifu/el2_ifu_mem_ctl.sv:34:-
design/ifu/el2_ifu_mem_ctl.sv:35:-   input logic                       exu_flush_final,               // Flush from the pipeline., includes flush lower
design/ifu/el2_ifu_mem_ctl.sv:36:-   input logic                       dec_tlu_flush_lower_wb,        // Flush lower from the pipeline.
design/ifu/el2_ifu_mem_ctl.sv:37:-   input logic                       dec_tlu_flush_err_wb,          // Flush from the pipeline due to perr.
design/ifu/el2_ifu_mem_ctl.sv:38:-   input logic                       dec_tlu_i0_commit_cmt,         // committed i0 instruction
design/ifu/el2_ifu_mem_ctl.sv:39:-   input logic                       dec_tlu_force_halt,            // force halt.
design/ifu/el2_ifu_mem_ctl.sv:40:-
design/ifu/el2_ifu_mem_ctl.sv:41:-   input logic [31:1]                ifc_fetch_addr_bf,             // Fetch Address byte aligned always.      F1 stage.
design/ifu/el2_ifu_mem_ctl.sv:42:-   input logic                       ifc_fetch_uncacheable_bf,      // The fetch request is uncacheable space. F1 stage
design/ifu/el2_ifu_mem_ctl.sv:43:-   input logic                       ifc_fetch_req_bf,              // Fetch request. Comes with the address.  F1 stage
design/ifu/el2_ifu_mem_ctl.sv:44:-   input logic                       ifc_fetch_req_bf_raw,          // Fetch request without some qualifications. Used for clock-gating. F1 stage
design/ifu/el2_ifu_mem_ctl.sv:45:-   input logic                       ifc_iccm_access_bf,            // This request is to the ICCM. Do not generate misses to the bus.
design/ifu/el2_ifu_mem_ctl.sv:46:-   input logic                       ifc_region_acc_fault_bf,       // Access fault. in ICCM region but offset is outside defined ICCM.
design/ifu/el2_ifu_mem_ctl.sv:47:-   input logic                       ifc_dma_access_ok,             // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle).
design/ifu/el2_ifu_mem_ctl.sv:48:-   input logic                       dec_tlu_fence_i_wb,            // Fence.i instruction is committing. Clear all Icache valids.
design/ifu/el2_ifu_mem_ctl.sv:49:-   input logic                       ifu_bp_hit_taken_f,            // Branch is predicted taken. Kill the fetch next cycle.
design/ifu/el2_ifu_mem_ctl.sv:50:-
design/ifu/el2_ifu_mem_ctl.sv:51:-   input logic                       ifu_bp_inst_mask_f,            // tell ic which valids to kill because of a taken branch, right justified
design/ifu/el2_ifu_mem_ctl.sv:52:-
design/ifu/el2_ifu_mem_ctl.sv:53:-   output logic                      ifu_miss_state_idle,           // No icache misses are outstanding.
design/ifu/el2_ifu_mem_ctl.sv:54:-   output logic                      ifu_ic_mb_empty,               // Continue with normal fetching. This does not mean that miss is finished.
design/ifu/el2_ifu_mem_ctl.sv:55:-   output logic                      ic_dma_active  ,               // In the middle of servicing dma request to ICCM. Do not make any new requests.
design/ifu/el2_ifu_mem_ctl.sv:56:-   output logic                      ic_write_stall,                // Stall fetch the cycle we are writing th
)
(
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
Expand Down Expand Up @@ -283,11 +283,6 @@
logic sel_mb_status_addr ;
logic [63:0] ic_final_data;

logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_ic_rw_int_addr_ff ;
logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_status_wr_addr_ff ;
logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_ic_rw_int_addr_w_debug ;
logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_status_wr_addr_w_debug ;

logic [pt.ICACHE_STATUS_BITS-1:0] way_status_new_ff ;
logic way_status_wr_en_ff ;
logic [pt.ICACHE_TAG_DEPTH-1:0][pt.ICACHE_STATUS_BITS-1:0] way_status_out ;
Expand Down Expand Up @@ -911,24 +906,19 @@
assign ic_miss_buff_half[63:0] = {ic_miss_buff_data[{other_tag,1'b1}],ic_miss_buff_data[{other_tag,1'b0}] } ;


/////////////////////////////////////////////////////////////////////////////////////

Check warning on line 909 in design/ifu/el2_ifu_mem_ctl.sv

View workflow job for this annotation

GitHub Actions / format-review 

[verible-verilog-format] reported by reviewdog 🐶


Raw Output:
design/ifu/el2_ifu_mem_ctl.sv:909:-/////////////////////////////////////////////////////////////////////////////////////
design/ifu/el2_ifu_mem_ctl.sv:910:-// Parity checking logic for Icache logic.                                         //
design/ifu/el2_ifu_mem_ctl.sv:911:-/////////////////////////////////////////////////////////////////////////////////////
design/ifu/el2_ifu_mem_ctl.sv:1047:+  /////////////////////////////////////////////////////////////////////////////////////
design/ifu/el2_ifu_mem_ctl.sv:1048:+  // Parity checking logic for Icache logic.                                         //
design/ifu/el2_ifu_mem_ctl.sv:1049:+  /////////////////////////////////////////////////////////////////////////////////////
// Parity checking logic for Icache logic. //
/////////////////////////////////////////////////////////////////////////////////////


assign ic_rd_parity_final_err = ic_tag_perr & ~exu_flush_final & sel_ic_data & ~(ifc_region_acc_fault_final_f | (|ifc_bus_acc_fault_f)) &
assign ic_rd_parity_final_err = ic_tag_perr & ~exu_flush_final & sel_ic_data & ~(ifc_region_acc_fault_final_f | (|ifc_bus_acc_fault_f)) &
(fetch_req_icache_f & ~reset_all_tags & (~miss_pending | (miss_state==HIT_U_MISS)) & ~sel_mb_addr_ff);

logic [pt.ICACHE_NUM_WAYS-1:0] perr_err_inv_way;
logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] perr_ic_index_ff;
logic perr_sel_invalidate;
logic perr_sb_write_status ;



rvdffe #(.WIDTH(pt.ICACHE_INDEX_HI-pt.ICACHE_TAG_INDEX_LO+1),.OVERRIDE(1)) perr_dat_ff (.din(ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO]), .dout(perr_ic_index_ff[pt.ICACHE_INDEX_HI : pt.ICACHE_TAG_INDEX_LO]), .en(perr_sb_write_status), .*);
logic [pt.ICACHE_NUM_WAYS-1:0] perr_err_inv_way;
logic perr_sel_invalidate;
logic perr_sb_write_status;
koluckirafal marked this conversation as resolved.
Show resolved Hide resolved

assign perr_err_inv_way[pt.ICACHE_NUM_WAYS-1:0] = {pt.ICACHE_NUM_WAYS{perr_sel_invalidate}} ;

Check warning on line 921 in design/ifu/el2_ifu_mem_ctl.sv

View workflow job for this annotation

GitHub Actions / format-review 

[verible-verilog-format] reported by reviewdog 🐶


Raw Output:
design/ifu/el2_ifu_mem_ctl.sv:921:-   assign perr_err_inv_way[pt.ICACHE_NUM_WAYS-1:0]   =  {pt.ICACHE_NUM_WAYS{perr_sel_invalidate}} ;
design/ifu/el2_ifu_mem_ctl.sv:922:-   assign iccm_correct_ecc     = (perr_state == ECC_CORR);
design/ifu/el2_ifu_mem_ctl.sv:923:-   assign dma_sb_err_state     = (perr_state == DMA_SB_ERR);
design/ifu/el2_ifu_mem_ctl.sv:924:-   assign iccm_buf_correct_ecc = iccm_correct_ecc & ~dma_sb_err_state_ff;
design/ifu/el2_ifu_mem_ctl.sv:1059:+  assign perr_err_inv_way[pt.ICACHE_NUM_WAYS-1:0] = {pt.ICACHE_NUM_WAYS{perr_sel_invalidate}};
design/ifu/el2_ifu_mem_ctl.sv:1060:+  assign iccm_correct_ecc                         = (perr_state == ECC_CORR);
design/ifu/el2_ifu_mem_ctl.sv:1061:+  assign dma_sb_err_state                         = (perr_state == DMA_SB_ERR);
design/ifu/el2_ifu_mem_ctl.sv:1062:+  assign iccm_buf_correct_ecc                     = iccm_correct_ecc & ~dma_sb_err_state_ff;
assign iccm_correct_ecc = (perr_state == ECC_CORR);
assign dma_sb_err_state = (perr_state == DMA_SB_ERR);
assign iccm_buf_correct_ecc = iccm_correct_ecc & ~dma_sb_err_state_ff;
Expand All @@ -942,44 +932,44 @@
//////////////////////////////////// Create Parity Error State Machine ///////////////////////


// FIFO state machine

Check warning on line 935 in design/ifu/el2_ifu_mem_ctl.sv

View workflow job for this annotation

GitHub Actions / format-review 

[verible-verilog-format] reported by reviewdog 🐶


Raw Output:
design/ifu/el2_ifu_mem_ctl.sv:935:-   // FIFO state machine
design/ifu/el2_ifu_mem_ctl.sv:936:-   always_comb begin  : ERROR_SM
design/ifu/el2_ifu_mem_ctl.sv:937:-      perr_nxtstate            = ERR_IDLE;
design/ifu/el2_ifu_mem_ctl.sv:938:-      perr_state_en            = 1'b0;
design/ifu/el2_ifu_mem_ctl.sv:939:-      perr_sel_invalidate      = 1'b0;
design/ifu/el2_ifu_mem_ctl.sv:940:-      perr_sb_write_status     = 1'b0;
design/ifu/el2_ifu_mem_ctl.sv:1073:+  // FIFO state machine
design/ifu/el2_ifu_mem_ctl.sv:1074:+  always_comb begin : ERROR_SM
design/ifu/el2_ifu_mem_ctl.sv:1075:+    perr_nxtstate        = ERR_IDLE;
design/ifu/el2_ifu_mem_ctl.sv:1076:+    perr_state_en        = 1'b0;
design/ifu/el2_ifu_mem_ctl.sv:1077:+    perr_sel_invalidate  = 1'b0;
design/ifu/el2_ifu_mem_ctl.sv:1078:+    perr_sb_write_status = 1'b0;
always_comb begin : ERROR_SM
perr_nxtstate = ERR_IDLE;
perr_state_en = 1'b0;
perr_sb_write_status = 1'b0;
perr_sel_invalidate = 1'b0;
perr_sb_write_status = 1'b0;
koluckirafal marked this conversation as resolved.
Show resolved Hide resolved

case (perr_state)
ERR_IDLE: begin : err_idle
perr_nxtstate = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
perr_state_en = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
perr_sb_write_status = perr_state_en;
end
IC_WFF: begin : icache_wff // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
perr_nxtstate = ERR_IDLE ;
perr_state_en = dec_tlu_flush_lower_wb | dec_tlu_force_halt ;
perr_sel_invalidate = (dec_tlu_flush_err_wb & dec_tlu_flush_lower_wb);
end
ECC_WFF: begin : ecc_wff
perr_nxtstate = ((~dec_tlu_flush_err_wb & dec_tlu_flush_lower_wb ) | dec_tlu_force_halt) ? ERR_IDLE : ECC_CORR ;
perr_state_en = dec_tlu_flush_lower_wb | dec_tlu_force_halt ;
end
DMA_SB_ERR : begin : dma_sb_ecc
perr_nxtstate = dec_tlu_force_halt ? ERR_IDLE : ECC_CORR;
perr_state_en = 1'b1;
end
ECC_CORR: begin : ecc_corr
perr_nxtstate = ERR_IDLE ;
perr_state_en = 1'b1 ;
end
default: begin : def_case
perr_nxtstate = ERR_IDLE;
perr_state_en = 1'b0;
perr_sb_write_status = 1'b0;
perr_sel_invalidate = 1'b0;
end
endcase
case (perr_state)
ERR_IDLE: begin : err_idle
perr_nxtstate = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
perr_state_en = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
perr_sb_write_status = perr_state_en;
end
IC_WFF: begin : icache_wff // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
perr_nxtstate = ERR_IDLE;
perr_state_en = dec_tlu_flush_lower_wb | dec_tlu_force_halt;
perr_sel_invalidate = (dec_tlu_flush_err_wb & dec_tlu_flush_lower_wb);
end
ECC_WFF: begin : ecc_wff
perr_nxtstate = ((~dec_tlu_flush_err_wb & dec_tlu_flush_lower_wb ) | dec_tlu_force_halt) ? ERR_IDLE : ECC_CORR;
perr_state_en = dec_tlu_flush_lower_wb | dec_tlu_force_halt;
end
DMA_SB_ERR: begin : dma_sb_ecc
perr_nxtstate = dec_tlu_force_halt ? ERR_IDLE : ECC_CORR;
perr_state_en = 1'b1;
end
ECC_CORR: begin : ecc_corr
perr_nxtstate = ERR_IDLE;
perr_state_en = 1'b1;
end
default: begin : def_case
perr_nxtstate = ERR_IDLE;
perr_state_en = 1'b0;
perr_sel_invalidate = 1'b0;
perr_sb_write_status = 1'b0;
end
endcase
end

Check warning on line 972 in design/ifu/el2_ifu_mem_ctl.sv

View workflow job for this annotation

GitHub Actions / format-review 

[verible-verilog-format] reported by reviewdog 🐶


Raw Output:
design/ifu/el2_ifu_mem_ctl.sv:972:-   end
design/ifu/el2_ifu_mem_ctl.sv:973:-
design/ifu/el2_ifu_mem_ctl.sv:974:-   rvdffs #(($bits(perr_state_t))) perr_state_ff (.clk(active_clk), .din(perr_nxtstate), .dout({perr_state}), .en(perr_state_en),   .*);
design/ifu/el2_ifu_mem_ctl.sv:975:-
design/ifu/el2_ifu_mem_ctl.sv:976:-   //////////////////////////////////// Create stop fetch State Machine /////////////////////////
design/ifu/el2_ifu_mem_ctl.sv:977:-   //////////////////////////////////// Create stop fetch State Machine /////////////////////////
design/ifu/el2_ifu_mem_ctl.sv:978:-   //////////////////////////////////// Create stop fetch State Machine /////////////////////////
design/ifu/el2_ifu_mem_ctl.sv:979:-   //////////////////////////////////// Create stop fetch State Machine /////////////////////////
design/ifu/el2_ifu_mem_ctl.sv:980:-   //////////////////////////////////// Create stop fetch State Machine /////////////////////////
design/ifu/el2_ifu_mem_ctl.sv:981:-   always_comb begin  : ERROR_STOP_FETCH
design/ifu/el2_ifu_mem_ctl.sv:982:-      err_stop_nxtstate            = ERR_STOP_IDLE;
design/ifu/el2_ifu_mem_ctl.sv:983:-      err_stop_state_en            = 1'b0;
design/ifu/el2_ifu_mem_ctl.sv:984:-      err_stop_fetch               = 1'b0;
design/ifu/el2_ifu_mem_ctl.sv:985:-      iccm_correction_state        = 1'b0;
design/ifu/el2_ifu_mem_ctl.sv:986:-
design/ifu/el2_ifu_mem_ctl.sv:987:-      case (err_stop_state)
design/ifu/el2_ifu_mem_ctl.sv:988:-         ERR_STOP_IDLE: begin : err_stop_idle
design/ifu/el2_ifu_mem_ctl.sv:989:-                  err_stop_nxtstate         =  ERR_FETCH1;
design/ifu/el2_ifu_mem_ctl.sv:990:-                  err_stop_state_en         =  dec_tlu_flush_err_wb & (perr_state  == ECC_WFF) & ~dec_tlu_force_halt;
design/ifu/el2_ifu_mem_ctl.sv:991:-         end
design/ifu/el2_ifu_mem_ctl.sv:992:-         ERR_FETCH1: begin : err_fetch1    // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state
design/ifu/el2_ifu_mem_ctl.sv:993:-                  err_stop_nxtstate       =  (dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt | dec_tlu_force_halt) ? ERR_STOP_IDLE : ((ifu_fetch_val[1:0] == 2'b11) | (ifu_fetch_val[0] & two_byte_instr))   ?  ERR_STOP_FETCH : ifu_fetch_val[0] ? ERR_FETCH2 :  ERR_FETCH1;
design/ifu/el2_ifu_mem_ctl.sv:994:-                  err_stop_state_en       =   dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt | ifu_fetch_val[0] | ifu_bp_hit_taken_q_f | dec_tlu_force_halt;
design/ifu/el2_ifu_mem_ctl.sv:995:-                  err_stop_fetch          =   ((ifu_fetch_val[1:0] == 2'b11) | (ifu_fetch_val[0] & two_byte_instr))  & ~(exu_flush_final | dec_tlu_i0_commit_cmt);
design/ifu/el2_ifu_mem_ctl.sv:996:-                  iccm_correction_state   = 1'b1;
design/ifu/el2_ifu_mem_ctl.sv:1110:+  end

rvdffs #(($bits(perr_state_t))) perr_state_ff (.clk(active_clk), .din(perr_nxtstate), .dout({perr_state}), .en(perr_state_en), .*);

Expand Down Expand Up @@ -1393,14 +1383,30 @@



///////////////////////////////////////////////////////////////

Check warning on line 1386 in design/ifu/el2_ifu_mem_ctl.sv

View workflow job for this annotation

GitHub Actions / format-review 

[verible-verilog-format] reported by reviewdog 🐶


Raw Output:
design/ifu/el2_ifu_mem_ctl.sv:1386:-///////////////////////////////////////////////////////////////
design/ifu/el2_ifu_mem_ctl.sv:1387:-// Icache status and LRU
design/ifu/el2_ifu_mem_ctl.sv:1388:-///////////////////////////////////////////////////////////////
design/ifu/el2_ifu_mem_ctl.sv:1389:-logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid_unq;
design/ifu/el2_ifu_mem_ctl.sv:1390:-if (pt.ICACHE_ENABLE == 1 ) begin: icache_enabled
design/ifu/el2_ifu_mem_ctl.sv:1391:-   logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_status_wr_addr_w_debug;
design/ifu/el2_ifu_mem_ctl.sv:1392:-   logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_status_wr_addr_ff ;
design/ifu/el2_ifu_mem_ctl.sv:1393:-   logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_ic_rw_int_addr_w_debug;
design/ifu/el2_ifu_mem_ctl.sv:1394:-   logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_ic_rw_int_addr_ff;
design/ifu/el2_ifu_mem_ctl.sv:1395:-   logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] perr_ic_index_ff;
design/ifu/el2_ifu_mem_ctl.sv:1673:+  ///////////////////////////////////////////////////////////////
design/ifu/el2_ifu_mem_ctl.sv:1674:+  // Icache status and LRU
design/ifu/el2_ifu_mem_ctl.sv:1675:+  ///////////////////////////////////////////////////////////////
design/ifu/el2_ifu_mem_ctl.sv:1676:+  logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid_unq;
design/ifu/el2_ifu_mem_ctl.sv:1677:+  if (pt.ICACHE_ENABLE == 1) begin : icache_enabled
design/ifu/el2_ifu_mem_ctl.sv:1678:+    logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_status_wr_addr_w_debug;
design/ifu/el2_ifu_mem_ctl.sv:1679:+    logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_status_wr_addr_ff;
design/ifu/el2_ifu_mem_ctl.sv:1680:+    logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_ic_rw_int_addr_w_debug;
design/ifu/el2_ifu_mem_ctl.sv:1681:+    logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_ic_rw_int_addr_ff;
design/ifu/el2_ifu_mem_ctl.sv:1682:+    logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] perr_ic_index_ff;
// Icache status and LRU
///////////////////////////////////////////////////////////////
logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid_unq;
if (pt.ICACHE_ENABLE == 1 ) begin: icache_enabled
assign ic_valid = ~ifu_wr_cumulative_err_data & ~(reset_ic_in | reset_ic_ff) & ~reset_tag_valid_for_miss;

assign ifu_status_wr_addr_w_debug[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] = ((ic_debug_rd_en | ic_debug_wr_en ) & ic_debug_tag_array) ?
logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_status_wr_addr_w_debug;
logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_status_wr_addr_ff ;
logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_ic_rw_int_addr_w_debug;
logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] ifu_ic_rw_int_addr_ff;
logic [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] perr_ic_index_ff;

rvdffe #(
.WIDTH(pt.ICACHE_INDEX_HI - pt.ICACHE_TAG_INDEX_LO + 1),
.OVERRIDE(1)
) perr_dat_ff (
.din (ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO]),
.dout(perr_ic_index_ff[pt.ICACHE_INDEX_HI : pt.ICACHE_TAG_INDEX_LO]),
.en (perr_sb_write_status),
.*
);

assign ic_valid = ~ifu_wr_cumulative_err_data & ~(reset_ic_in | reset_ic_ff) & ~reset_tag_valid_for_miss;

assign ifu_status_wr_addr_w_debug[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] = ((ic_debug_rd_en | ic_debug_wr_en ) & ic_debug_tag_array) ?
ic_debug_addr[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] :
ifu_status_wr_addr[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO];

Expand Down