Use RISC-V DV for core verification #79
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…nd in spike ISS Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
…d it with the Makefile flow Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
…truction Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
…nt path Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
…py, added matrix CI Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
…ion attempts writing to x0 (zero) Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
mkurc-ant
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This PR introduces the use of RISC-V DV framework for testing VeeR-EL2 core.
The flow uses a custom Makefile located in
tools/riscv-dv. The makefile invokes therun.pyscript which generates a random instruction stream for a given test, compiles it and runs in a ISS. Currentlyspikeandveer-issare supported by the makefile. The other part of the makefile is responsible for building verilated testbench for VeeR and running the same compiled code. The last part is execution log comparison using an utility from RISC-V DV.Since RISC-V DV uses its own format of execution log (CSV) it was necessary to write a log converter for VeeR to adapt execution logs produced by testbench.
The PR also includes a GH action CI flow which builds all the dependencies (
verilator,spike, andveer-iss) and runs the tests. The tests are organized in a matrix which tests all combinations of ISS and test. Currently there is only one test and two ISSes.