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Merge pull request #3953 from alainmarcel/alainmarcel-patch-1
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file level param binding
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@alaindargelas
alaindargelas committed Jan 12, 2024
2 parents f687293 + 1b890bf commit a2a7f29
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Showing 9 changed files with 306 additions and 21 deletions.
1 change: 1 addition & 0 deletions include/Surelog/DesignCompile/UhdmWriter.h
View file
Expand Up @@ -131,6 +131,7 @@ class UhdmWriter final {

CompileDesign* const m_compileDesign;
Design* const m_design;
UHDM::design* m_uhdmDesign;
ComponentMap m_componentMap;
CompileHelper m_helper;
};
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16 changes: 15 additions & 1 deletion src/DesignCompile/UhdmWriter.cpp
View file
Expand Up @@ -165,7 +165,7 @@ std::string UhdmWriter::builtinGateName(VObjectType type) {
}

UhdmWriter::UhdmWriter(CompileDesign* compiler, Design* design)
: m_compileDesign(compiler), m_design(design) {
: m_compileDesign(compiler), m_design(design), m_uhdmDesign(nullptr) {
m_helper.seterrorReporting(
m_compileDesign->getCompiler()->getErrorContainer(),
m_compileDesign->getCompiler()->getSymbolTable());
Expand Down Expand Up @@ -3723,6 +3723,19 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) {
if (ref->Actual_group()) break;
}
}

if (!ref->Actual_group()) {
design* d = m_uhdmDesign;
if (auto params = d->Parameters()) {
for (auto decl : *params) {
if (decl->VpiName() == name) {
ref->Actual_group(decl);
break;
}
}
}
}

if (!ref->Actual_group()) {
if (mod) {
if (auto elem = mod->getDesignElement()) {
Expand Down Expand Up @@ -4696,6 +4709,7 @@ vpiHandle UhdmWriter::write(PathId uhdmFileId) {
design* d = nullptr;
if (m_design) {
d = s.MakeDesign();
m_uhdmDesign = d;
designHandle = reinterpret_cast<vpiHandle>(new uhdm_handle(uhdmdesign, d));
std::string designName = "unnamed";
auto topLevelModules = m_design->getTopLevelModuleInstances();
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16 changes: 0 additions & 16 deletions tests/ConstCapital/ConstCapital.log
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Expand Up @@ -131,7 +131,6 @@ gen_if 2
gen_scope 4
gen_scope_array 4
int_typespec 7
logic_net 2
module_inst 7
operation 4
param_assign 4
Expand All @@ -149,7 +148,6 @@ gen_if 2
gen_scope 6
gen_scope_array 6
int_typespec 7
logic_net 2
module_inst 9
operation 4
param_assign 4
Expand Down Expand Up @@ -178,20 +176,6 @@ design: (work@test)
\_design: (work@test)
|vpiFullName:work@test
|vpiDefName:work@test
|vpiNet:
\_logic_net: (work@test.foo), line:10:5, endln:10:8
|vpiParent:
\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ConstCapital/dut.sv, line:8:1, endln:19:10
|vpiName:foo
|vpiFullName:work@test.foo
|vpiNetType:1
|vpiNet:
\_logic_net: (work@test.foo2), line:15:5, endln:15:9
|vpiParent:
\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ConstCapital/dut.sv, line:8:1, endln:19:10
|vpiName:foo2
|vpiFullName:work@test.foo2
|vpiNetType:1
|vpiGenStmt:
\_gen_if: , line:10:1, endln:10:3
|vpiParent:
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274 changes: 274 additions & 0 deletions tests/FileLocalParam/FileLocalParam.log
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@@ -0,0 +1,274 @@
[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/FileLocalParam/slpp_all/surelog.log".
AST_DEBUG_BEGIN
LIB: work
FILE: ${SURELOG_DIR}/tests/FileLocalParam/dut.sv
n<> u<0> t<_INVALID_> f<0> l<0:0>
n<> u<1> t<Null_rule> p<69> s<68> l<1:1> el<1:0>
n<> u<2> t<Data_type_or_implicit> p<12> s<11> l<1:25> el<1:25>
n<AWIDTH> u<3> t<StringConst> p<10> s<9> l<1:25> el<1:31>
n<16> u<4> t<IntConst> p<5> l<1:56> el<1:58>
n<> u<5> t<Primary_literal> p<6> c<4> l<1:56> el<1:58>
n<> u<6> t<Constant_primary> p<7> c<5> l<1:56> el<1:58>
n<> u<7> t<Constant_expression> p<8> c<6> l<1:56> el<1:58>
n<> u<8> t<Constant_mintypmax_expression> p<9> c<7> l<1:56> el<1:58>
n<> u<9> t<Constant_param_expression> p<10> c<8> l<1:56> el<1:58>
n<> u<10> t<Param_assignment> p<11> c<3> l<1:25> el<1:58>
n<> u<11> t<List_of_param_assignments> p<12> c<10> l<1:25> el<1:58>
n<> u<12> t<Local_parameter_declaration> p<13> c<2> l<1:1> el<1:58>
n<> u<13> t<Package_or_generate_item_declaration> p<14> c<12> l<1:1> el<1:60>
n<> u<14> t<Package_item> p<15> c<13> l<1:1> el<1:60>
n<> u<15> t<Description> p<68> c<14> s<42> l<1:1> el<1:60>
n<AWIDTH> u<16> t<StringConst> p<17> l<3:13> el<3:19>
n<> u<17> t<Primary_literal> p<18> c<16> l<3:13> el<3:19>
n<> u<18> t<Constant_primary> p<19> c<17> l<3:13> el<3:19>
n<> u<19> t<Constant_expression> p<24> c<18> s<23> l<3:13> el<3:19>
n<0> u<20> t<IntConst> p<21> l<3:20> el<3:21>
n<> u<21> t<Primary_literal> p<22> c<20> l<3:20> el<3:21>
n<> u<22> t<Constant_primary> p<23> c<21> l<3:20> el<3:21>
n<> u<23> t<Constant_expression> p<24> c<22> l<3:20> el<3:21>
n<> u<24> t<Constant_range> p<25> c<19> l<3:13> el<3:21>
n<> u<25> t<Packed_dimension> p<26> c<24> l<3:12> el<3:22>
n<> u<26> t<Data_type_or_implicit> p<39> c<25> s<38> l<3:12> el<3:22>
n<MAP> u<27> t<StringConst> p<37> s<36> l<3:23> el<3:26>
n<AWIDTH> u<28> t<StringConst> p<29> l<4:3> el<4:9>
n<> u<29> t<Primary_literal> p<30> c<28> l<4:3> el<4:9>
n<> u<30> t<Constant_primary> p<31> c<29> l<4:3> el<4:9>
n<> u<31> t<Constant_expression> p<32> c<30> l<4:3> el<4:9>
n<> u<32> t<Constant_concatenation> p<33> c<31> l<3:33> el<5:48>
n<> u<33> t<Constant_primary> p<34> c<32> l<3:33> el<5:48>
n<> u<34> t<Constant_expression> p<35> c<33> l<3:33> el<5:48>
n<> u<35> t<Constant_mintypmax_expression> p<36> c<34> l<3:33> el<5:48>
n<> u<36> t<Constant_param_expression> p<37> c<35> l<3:33> el<5:48>
n<> u<37> t<Param_assignment> p<38> c<27> l<3:23> el<5:48>
n<> u<38> t<List_of_param_assignments> p<39> c<37> l<3:23> el<5:48>
n<> u<39> t<Local_parameter_declaration> p<40> c<26> l<3:1> el<5:48>
n<> u<40> t<Package_or_generate_item_declaration> p<41> c<39> l<3:1> el<5:49>
n<> u<41> t<Package_item> p<42> c<40> l<3:1> el<5:49>
n<> u<42> t<Description> p<68> c<41> s<67> l<3:1> el<5:49>
n<module> u<43> t<Module_keyword> p<47> s<44> l<7:1> el<7:7>
n<top> u<44> t<StringConst> p<47> s<46> l<7:8> el<7:11>
n<> u<45> t<Port> p<46> l<7:12> el<7:12>
n<> u<46> t<List_of_ports> p<47> c<45> l<7:11> el<7:13>
n<> u<47> t<Module_nonansi_header> p<66> c<43> s<64> l<7:1> el<7:14>
n<> u<48> t<Data_type_or_implicit> p<58> s<57> l<9:13> el<9:13>
n<D> u<49> t<StringConst> p<56> s<55> l<9:13> el<9:14>
n<MAP> u<50> t<StringConst> p<51> l<9:16> el<9:19>
n<> u<51> t<Primary_literal> p<52> c<50> l<9:16> el<9:19>
n<> u<52> t<Constant_primary> p<53> c<51> l<9:16> el<9:19>
n<> u<53> t<Constant_expression> p<54> c<52> l<9:16> el<9:19>
n<> u<54> t<Constant_mintypmax_expression> p<55> c<53> l<9:16> el<9:19>
n<> u<55> t<Constant_param_expression> p<56> c<54> l<9:16> el<9:19>
n<> u<56> t<Param_assignment> p<57> c<49> l<9:13> el<9:19>
n<> u<57> t<List_of_param_assignments> p<58> c<56> l<9:13> el<9:19>
n<> u<58> t<Parameter_declaration> p<59> c<48> l<9:3> el<9:19>
n<> u<59> t<Package_or_generate_item_declaration> p<60> c<58> l<9:3> el<9:20>
n<> u<60> t<Module_or_generate_item_declaration> p<61> c<59> l<9:3> el<9:20>
n<> u<61> t<Module_common_item> p<62> c<60> l<9:3> el<9:20>
n<> u<62> t<Module_or_generate_item> p<63> c<61> l<9:3> el<9:20>
n<> u<63> t<Non_port_module_item> p<64> c<62> l<9:3> el<9:20>
n<> u<64> t<Module_item> p<66> c<63> s<65> l<9:3> el<9:20>
n<> u<65> t<ENDMODULE> p<66> l<11:1> el<11:10>
n<> u<66> t<Module_declaration> p<67> c<47> l<7:1> el<11:10>
n<> u<67> t<Description> p<68> c<66> l<7:1> el<11:10>
n<> u<68> t<Source_text> p<69> c<15> l<1:1> el<11:10>
n<> u<69> t<Top_level_rule> c<1> l<1:1> el<11:10>
AST_DEBUG_END
[WRN:PA0205] ${SURELOG_DIR}/tests/FileLocalParam/dut.sv:7:1: No timescale set for "top".
[INF:CP0300] Compilation...
[INF:CP0303] ${SURELOG_DIR}/tests/FileLocalParam/dut.sv:7:1: Compile module "work@top".
[INF:EL0526] Design Elaboration...
[NTE:EL0503] ${SURELOG_DIR}/tests/FileLocalParam/dut.sv:7:1: Top level module "work@top".
[NTE:EL0508] Nb Top level modules: 1.
[NTE:EL0509] Max instance depth: 1.
[NTE:EL0510] Nb instances: 1.
[NTE:EL0511] Nb leaf instances: 1.
[INF:UH0706] Creating UHDM Model...
=== UHDM Object Stats Begin (Non-Elaborated Model) ===
constant 7
design 1
int_typespec 5
module_inst 5
operation 3
param_assign 6
parameter 6
range 2
ref_obj 6
ref_typespec 8
=== UHDM Object Stats End ===
[INF:UH0707] Elaborating UHDM...
=== UHDM Object Stats Begin (Elaborated Model) ===
constant 7
design 1
int_typespec 5
module_inst 5
operation 3
param_assign 6
parameter 6
range 2
ref_obj 6
ref_typespec 8
=== UHDM Object Stats End ===
[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/FileLocalParam/slpp_all/surelog.uhdm ...
[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/FileLocalParam/slpp_all/checker/surelog.chk.html ...
[INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}/build/regression/FileLocalParam/slpp_all/surelog.uhdm ...
[INF:UH0711] Decompiling UHDM...
====== UHDM =======
design: (work@top)
|vpiElaborated:1
|vpiName:work@top
|uhdmallModules:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:7:1, endln:11:10
|vpiParent:
\_design: (work@top)
|vpiFullName:work@top
|vpiParameter:
\_parameter: (work@top.D), line:9:13, endln:9:14
|vpiParent:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:7:1, endln:11:10
|vpiName:D
|vpiFullName:work@top.D
|vpiParamAssign:
\_param_assign: , line:9:13, endln:9:19
|vpiParent:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:7:1, endln:11:10
|vpiRhs:
\_ref_obj: (work@top.MAP), line:9:16, endln:9:19
|vpiParent:
\_param_assign: , line:9:13, endln:9:19
|vpiName:MAP
|vpiFullName:work@top.MAP
|vpiActual:
\_parameter: (MAP), line:3:23, endln:3:26
|vpiLhs:
\_parameter: (work@top.D), line:9:13, endln:9:14
|vpiDefName:work@top
|vpiParameter:
\_parameter: (AWIDTH), line:1:25, endln:1:31
|vpiParent:
\_design: (work@top)
|UINT:16
|vpiTypespec:
\_ref_typespec: (AWIDTH)
|vpiParent:
\_parameter: (AWIDTH), line:1:25, endln:1:31
|vpiFullName:AWIDTH
|vpiActual:
\_int_typespec: , line:1:1, endln:1:58
|vpiLocalParam:1
|vpiName:AWIDTH
|vpiParameter:
\_parameter: (MAP), line:3:23, endln:3:26
|vpiParent:
\_design: (work@top)
|vpiTypespec:
\_ref_typespec: (MAP)
|vpiParent:
\_parameter: (MAP), line:3:23, endln:3:26
|vpiFullName:MAP
|vpiActual:
\_int_typespec: , line:3:12, endln:3:22
|vpiLocalParam:1
|vpiName:MAP
|vpiParamAssign:
\_param_assign: , line:1:25, endln:1:58
|vpiParent:
\_design: (work@top)
|vpiRhs:
\_constant: , line:1:56, endln:1:58
|vpiParent:
\_param_assign: , line:1:25, endln:1:58
|vpiDecompile:16
|vpiSize:32
|UINT:16
|vpiTypespec:
\_ref_typespec:
|vpiParent:
\_constant: , line:1:56, endln:1:58
|vpiActual:
\_int_typespec: , line:1:1, endln:1:58
|vpiConstType:9
|vpiLhs:
\_parameter: (AWIDTH), line:1:25, endln:1:31
|vpiParamAssign:
\_param_assign: , line:3:23, endln:5:48
|vpiParent:
\_design: (work@top)
|vpiRhs:
\_operation: , line:3:33, endln:5:48
|vpiParent:
\_param_assign: , line:3:23, endln:5:48
|vpiOpType:33
|vpiOperand:
\_ref_obj: (AWIDTH), line:4:3, endln:4:9
|vpiParent:
\_operation: , line:3:33, endln:5:48
|vpiName:AWIDTH
|vpiLhs:
\_parameter: (MAP), line:3:23, endln:3:26
|uhdmtopModules:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:7:1, endln:11:10
|vpiName:work@top
|vpiParameter:
\_parameter: (work@top.D), line:9:13, endln:9:14
|vpiParent:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:7:1, endln:11:10
|vpiName:D
|vpiFullName:work@top.D
|vpiParamAssign:
\_param_assign: , line:9:13, endln:9:19
|vpiParent:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:7:1, endln:11:10
|vpiRhs:
\_ref_obj: (work@top.MAP), line:9:16, endln:9:19
|vpiParent:
\_param_assign: , line:9:13, endln:9:19
|vpiName:MAP
|vpiFullName:work@top.MAP
|vpiActual:
\_parameter: (MAP), line:3:23, endln:3:26
|vpiLhs:
\_parameter: (work@top.D), line:9:13, endln:9:14
|vpiDefName:work@top
|vpiTop:1
|vpiTopModule:1
\_weaklyReferenced:
\_int_typespec: , line:1:1, endln:1:58
\_int_typespec: , line:3:12, endln:3:22
|vpiParent:
\_parameter: (MAP), line:3:23, endln:3:26
|vpiRange:
\_range: , line:3:12, endln:3:22
|vpiParent:
\_int_typespec: , line:3:12, endln:3:22
|vpiLeftRange:
\_constant: , line:3:13, endln:3:19
|vpiParent:
\_range: , line:3:12, endln:3:22
|vpiDecompile:16
|vpiSize:32
|UINT:16
|vpiTypespec:
\_ref_typespec: (MAP)
|vpiParent:
\_constant: , line:3:13, endln:3:19
|vpiFullName:MAP
|vpiActual:
\_int_typespec: , line:1:1, endln:1:58
|vpiConstType:9
|vpiRightRange:
\_constant: , line:3:20, endln:3:21
|vpiParent:
\_range: , line:3:12, endln:3:22
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiConstType:9
\_int_typespec: , line:1:1, endln:1:58
|vpiParent:
\_ref_typespec: (MAP)
===================
[ FATAL] : 0
[ SYNTAX] : 0
[ ERROR] : 0
[WARNING] : 1
[ NOTE] : 5
1 change: 1 addition & 0 deletions tests/FileLocalParam/FileLocalParam.sl
View file
@@ -0,0 +1 @@
-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin
11 changes: 11 additions & 0 deletions tests/FileLocalParam/dut.sv
View file
@@ -0,0 +1,11 @@
localparam AWIDTH = 16 ;

localparam [AWIDTH:0] MAP ={
AWIDTH
};

module top();

parameter D =MAP;

endmodule
4 changes: 2 additions & 2 deletions third_party/tests/CoresSweRVMP/CoresSweRVMP.log
View file
Expand Up @@ -73,8 +73,8 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess;
[ 43%] Generating 16_dec_decode_ctl.sv
[ 50%] Generating 1_lsu_stbuf.sv
[ 56%] Generating 2_ahb_to_axi4.sv
[ 62%] Generating 3_rvjtag_tap.sv
[ 68%] Generating 4_dec_tlu_ctl.sv
[ 62%] Generating 4_dec_tlu_ctl.sv
[ 68%] Generating 3_rvjtag_tap.sv
[ 75%] Generating 5_lsu_bus_buffer.sv
[ 81%] Generating 6_dbg.sv
[ 87%] Generating 7_axi4_to_ahb.sv
Expand Down
2 changes: 1 addition & 1 deletion third_party/tests/Scr1/Scr1.log
View file
Expand Up @@ -259,7 +259,7 @@ int_var 40
integer_typespec 59
integer_var 3
io_decl 27
logic_net 2690
logic_net 2621
logic_typespec 4195
logic_var 828
method_func_call 5
Expand Down

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