Merge pull request #3892 from alainmarcel/alainmarcel-patch-1

Filter out timescale warning with -synth
chipsalliance · Sep 30, 2023 · d5f0e26 · d5f0e26
2 parents 09b8d6a + 6afc20e
commit d5f0e26
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Showing 9 changed files with 17 additions and 28 deletions.
diff --git a/src/SourceCompile/CheckCompile.cpp b/src/SourceCompile/CheckCompile.cpp
@@ -71,6 +71,8 @@ bool CheckCompile::mergeSymbolTables_() {
 bool CheckCompile::checkTimescale_() {
   std::string globaltimescale =
       m_compiler->getCommandLineParser()->getTimeScale();
+  bool reportMissingTimescale =
+      !m_compiler->getCommandLineParser()->reportNonSynthesizable();
   if (!globaltimescale.empty()) {
     Location loc(m_compiler->getSymbolTable()->registerSymbol(globaltimescale));
     Error err(ErrorDefinition::CMD_USING_GLOBAL_TIMESCALE, loc);
@@ -108,7 +110,8 @@ bool CheckCompile::checkTimescale_() {
               reportedMissingTimescale.end()) {
             reportedMissingTimescale.insert(elem->m_name);
             Error err(ErrorDefinition::PA_NOTIMESCALE_INFO, loc);
-            m_compiler->getErrorContainer()->addError(err);
+            if (reportMissingTimescale)
+              m_compiler->getErrorContainer()->addError(err);
           }
         }
       }

diff --git a/tests/DashYTest/DashYTest.log b/tests/DashYTest/DashYTest.log
@@ -91,10 +91,6 @@ n<> u<27> t<Description> p<28> c<26> l<1:1> el<6:10>
 n<> u<28> t<Source_text> p<29> c<27> l<1:1> el<6:10>
 n<> u<29> t<Top_level_rule> c<1> l<1:1> el<7:1>
 AST_DEBUG_END
-[WRN:PA0205] ${SURELOG_DIR}/tests/DashYTest/dut.sv:1:1: No timescale set for "top".
-[WRN:PA0205] ${SURELOG_DIR}/tests/DashYTest/lib/AND.v:1:1: No timescale set for "AND".
-[WRN:PA0205] ${SURELOG_DIR}/tests/DashYTest/lib/OR.v:1:1: No timescale set for "OR".
-[WRN:PA0205] ${SURELOG_DIR}/tests/DashYTest/lib/SIM.v:1:1: No timescale set for "SIM".
 [INF:CP0300] Compilation...
 [INF:CP0303] ${SURELOG_DIR}/tests/DashYTest/lib/AND.v:1:1: Compile module "work@AND".
 [INF:CP0303] ${SURELOG_DIR}/tests/DashYTest/lib/OR.v:1:1: Compile module "work@OR".
@@ -175,7 +171,7 @@ design: (work@top)
 [  FATAL] : 0
 [ SYNTAX] : 0
 [  ERROR] : 0
-[WARNING] : 4
+[WARNING] : 0
 [   NOTE] : 5
 
 ============================== Begin RoundTrip Results ==============================

diff --git a/tests/InsideOp/InsideOp.log b/tests/InsideOp/InsideOp.log
@@ -283,9 +283,6 @@ n<> u<277> t<Description> p<278> c<276> l<17:1> el<38:10>
 n<> u<278> t<Source_text> p<279> c<50> l<1:1> el<38:10>
 n<> u<279> t<Top_level_rule> c<1> l<1:1> el<39:1>
 AST_DEBUG_END
-[WRN:PA0205] ${SURELOG_DIR}/tests/InsideOp/dut.sv:1:1: No timescale set for "my_pkg".
-[WRN:PA0205] ${SURELOG_DIR}/tests/InsideOp/dut.sv:14:1: No timescale set for "GOOD".
-[WRN:PA0205] ${SURELOG_DIR}/tests/InsideOp/dut.sv:17:1: No timescale set for "top".
 [INF:CP0300] Compilation...
 [INF:CP0301] ${SURELOG_DIR}/tests/InsideOp/dut.sv:1:1: Compile package "my_pkg".
 [INF:CP0303] ${SURELOG_DIR}/tests/InsideOp/dut.sv:14:1: Compile module "work@GOOD".
@@ -1050,7 +1047,7 @@ design: (work@top)
 [  FATAL] : 0
 [ SYNTAX] : 0
 [  ERROR] : 0
-[WARNING] : 3
+[WARNING] : 0
 [   NOTE] : 5
 
 ============================== Begin RoundTrip Results ==============================

diff --git a/tests/NonSynthError/NonSynthError.log b/tests/NonSynthError/NonSynthError.log
@@ -62,7 +62,6 @@ n<> u<56> t<Description> p<57> c<55> l<2:1> el<13:10>
 n<> u<57> t<Source_text> p<58> c<56> l<2:1> el<13:10>
 n<> u<58> t<Top_level_rule> c<1> l<2:1> el<14:1>
 AST_DEBUG_END
-[WRN:PA0205] ${SURELOG_DIR}/tests/NonSynthError/dut.sv:2:1: No timescale set for "dut".
 [INF:CP0300] Compilation...
 [INF:CP0303] ${SURELOG_DIR}/tests/NonSynthError/dut.sv:2:1: Compile module "work@dut".
 [INF:CP0302] ${SURELOG_DIR}/tests/NonSynthError/dut.sv:10:1: Compile class "work@dut::A".
@@ -230,7 +229,7 @@ design: (work@dut)
 [  FATAL] : 0
 [ SYNTAX] : 0
 [  ERROR] : 0
-[WARNING] : 2
+[WARNING] : 1
 [   NOTE] : 5
 
 ============================== Begin Linting Results ==============================

diff --git a/tests/NonSynthUnusedMod/NonSynthUnusedMod.log b/tests/NonSynthUnusedMod/NonSynthUnusedMod.log
@@ -84,9 +84,6 @@ n<> u<36> t<Description> p<37> c<35> l<1:1> el<7:10>
 n<> u<37> t<Source_text> p<38> c<36> l<1:1> el<7:10>
 n<> u<38> t<Top_level_rule> c<1> l<1:1> el<8:1>
 AST_DEBUG_END
-[WRN:PA0205] ${SURELOG_DIR}/tests/NonSynthUnusedMod/dut.sv:1:1: No timescale set for "dut".
-[WRN:PA0205] ${SURELOG_DIR}/tests/NonSynthUnusedMod/top.v:1:1: No timescale set for "top".
-[WRN:PA0205] ${SURELOG_DIR}/tests/NonSynthUnusedMod/nonsynth.v:1:1: No timescale set for "nonsynth".
 [INF:CP0300] Compilation...
 [INF:CP0303] ${SURELOG_DIR}/tests/NonSynthUnusedMod/dut.sv:1:1: Compile module "work@dut".
 [INF:CP0303] ${SURELOG_DIR}/tests/NonSynthUnusedMod/nonsynth.v:1:1: Compile module "work@nonsynth".
@@ -168,7 +165,7 @@ design: (work@dut)
 [  FATAL] : 0
 [ SYNTAX] : 0
 [  ERROR] : 0
-[WARNING] : 3
+[WARNING] : 0
 [   NOTE] : 5
 
 ============================== Begin RoundTrip Results ==============================

diff --git a/tests/PatternAssignment/PatternAssignment.log b/tests/PatternAssignment/PatternAssignment.log
@@ -121,7 +121,6 @@ n<> u<115> t<Description> p<116> c<114> l<1:1> el<15:10>
 n<> u<116> t<Source_text> p<117> c<115> l<1:1> el<15:10>
 n<> u<117> t<Top_level_rule> c<1> l<1:1> el<16:1>
 AST_DEBUG_END
-[WRN:PA0205] ${SURELOG_DIR}/tests/PatternAssignment/dut.sv:1:1: No timescale set for "dut".
 [INF:CP0300] Compilation...
 [INF:CP0303] ${SURELOG_DIR}/tests/PatternAssignment/dut.sv:1:1: Compile module "work@dut".
 [INF:EL0526] Design Elaboration...
@@ -554,7 +553,7 @@ design: (work@dut)
 [  FATAL] : 0
 [ SYNTAX] : 0
 [  ERROR] : 0
-[WARNING] : 1
+[WARNING] : 0
 [   NOTE] : 5
 
 ============================== Begin RoundTrip Results ==============================

diff --git a/tests/SynthFilterDollarError/SynthFilterDollarError.log b/tests/SynthFilterDollarError/SynthFilterDollarError.log
@@ -47,7 +47,6 @@ n<> u<41> t<Description> p<42> c<40> l<3:1> el<10:10>
 n<> u<42> t<Source_text> p<43> c<41> l<3:1> el<10:10>
 n<> u<43> t<Top_level_rule> c<1> l<3:1> el<11:1>
 AST_DEBUG_END
-[WRN:PA0205] ${SURELOG_DIR}/tests/SynthFilterDollarError/dut.sv:3:1: No timescale set for "top".
 [INF:CP0300] Compilation...
 [INF:CP0303] ${SURELOG_DIR}/tests/SynthFilterDollarError/dut.sv:3:1: Compile module "work@top".
 [ERR:CP0316] ${SURELOG_DIR}/tests/SynthFilterDollarError/dut.sv:4:10: Undefined package "pack".
@@ -124,7 +123,7 @@ design: (work@top)
 [  FATAL] : 0
 [ SYNTAX] : 0
 [  ERROR] : 2
-[WARNING] : 1
+[WARNING] : 0
 [   NOTE] : 5
 
 ============================== Begin RoundTrip Results ==============================

diff --git a/tests/TranslateOff/TranslateOff.log b/tests/TranslateOff/TranslateOff.log
@@ -47,7 +47,6 @@ n<> u<41> t<Description> p<42> c<40> l<10:1> el<23:10>
 n<> u<42> t<Source_text> p<43> c<41> l<10:1> el<23:10>
 n<> u<43> t<Top_level_rule> c<1> l<10:1> el<24:1>
 AST_DEBUG_END
-[WRN:PA0205] ${SURELOG_DIR}/tests/TranslateOff/dut.sv:10:1: No timescale set for "top".
 [INF:CP0300] Compilation...
 [INF:CP0303] ${SURELOG_DIR}/tests/TranslateOff/dut.sv:10:1: Compile module "work@top".
 [INF:EL0526] Design Elaboration...
@@ -204,7 +203,7 @@ design: (work@top)
 [  FATAL] : 0
 [ SYNTAX] : 0
 [  ERROR] : 0
-[WARNING] : 1
+[WARNING] : 0
 [   NOTE] : 5
 
 ============================== Begin RoundTrip Results ==============================

diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
@@ -80,12 +80,12 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required):
 -- Configuring done (0.1s)
 -- Generating done (0.0s)
 -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
-[  6%] Generating 10_lsu_bus_intf.sv
-[ 12%] Generating 11_ifu_bp_ctl.sv
-[ 18%] Generating 12_beh_lib.sv
-[ 25%] Generating 13_ifu_mem_ctl.sv
-[ 31%] Generating 14_mem_lib.sv
-[ 37%] Generating 15_exu.sv
+[ 12%] Generating 14_mem_lib.sv
+[ 12%] Generating 12_beh_lib.sv
+[ 18%] Generating 15_exu.sv
+[ 25%] Generating 11_ifu_bp_ctl.sv
+[ 31%] Generating 10_lsu_bus_intf.sv
+[ 37%] Generating 13_ifu_mem_ctl.sv
 [ 43%] Generating 16_dec_decode_ctl.sv
 [ 50%] Generating 1_lsu_stbuf.sv
 [ 56%] Generating 2_ahb_to_axi4.sv