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@alaindargelas
alaindargelas committed Jan 13, 2024
1 parent f2621ed commit fd6e404
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Showing 3 changed files with 195 additions and 75 deletions.
258 changes: 185 additions & 73 deletions tests/FileLocalParam/FileLocalParam.log
View file
Expand Up @@ -3,7 +3,7 @@ AST_DEBUG_BEGIN
LIB: work
FILE: ${SURELOG_DIR}/tests/FileLocalParam/dut.sv
n<> u<0> t<_INVALID_> f<0> l<0:0>
n<> u<1> t<Null_rule> p<69> s<68> l<1:1> el<1:0>
n<> u<1> t<Null_rule> p<106> s<105> l<1:1> el<1:0>
n<> u<2> t<Data_type_or_implicit> p<12> s<11> l<1:25> el<1:25>
n<AWIDTH> u<3> t<StringConst> p<10> s<9> l<1:25> el<1:31>
n<16> u<4> t<IntConst> p<5> l<1:56> el<1:58>
Expand All @@ -17,7 +17,7 @@ n<> u<11> t<List_of_param_assignments> p<12> c<10> l<1:25> el<1:58>
n<> u<12> t<Local_parameter_declaration> p<13> c<2> l<1:1> el<1:58>
n<> u<13> t<Package_or_generate_item_declaration> p<14> c<12> l<1:1> el<1:60>
n<> u<14> t<Package_item> p<15> c<13> l<1:1> el<1:60>
n<> u<15> t<Description> p<68> c<14> s<42> l<1:1> el<1:60>
n<> u<15> t<Description> p<105> c<14> s<42> l<1:1> el<1:60>
n<AWIDTH> u<16> t<StringConst> p<17> l<3:13> el<3:19>
n<> u<17> t<Primary_literal> p<18> c<16> l<3:13> el<3:19>
n<> u<18> t<Constant_primary> p<19> c<17> l<3:13> el<3:19>
Expand All @@ -44,69 +44,117 @@ n<> u<38> t<List_of_param_assignments> p<39> c<37> l<3:23> el<5:48>
n<> u<39> t<Local_parameter_declaration> p<40> c<26> l<3:1> el<5:48>
n<> u<40> t<Package_or_generate_item_declaration> p<41> c<39> l<3:1> el<5:49>
n<> u<41> t<Package_item> p<42> c<40> l<3:1> el<5:49>
n<> u<42> t<Description> p<68> c<41> s<67> l<3:1> el<5:49>
n<> u<42> t<Description> p<105> c<41> s<50> l<3:1> el<5:49>
n<module> u<43> t<Module_keyword> p<47> s<44> l<7:1> el<7:7>
n<top> u<44> t<StringConst> p<47> s<46> l<7:8> el<7:11>
n<> u<45> t<Port> p<46> l<7:12> el<7:12>
n<> u<46> t<List_of_ports> p<47> c<45> l<7:11> el<7:13>
n<> u<47> t<Module_nonansi_header> p<66> c<43> s<64> l<7:1> el<7:14>
n<> u<48> t<Data_type_or_implicit> p<58> s<57> l<9:13> el<9:13>
n<D> u<49> t<StringConst> p<56> s<55> l<9:13> el<9:14>
n<MAP> u<50> t<StringConst> p<51> l<9:16> el<9:19>
n<> u<51> t<Primary_literal> p<52> c<50> l<9:16> el<9:19>
n<> u<52> t<Constant_primary> p<53> c<51> l<9:16> el<9:19>
n<> u<53> t<Constant_expression> p<54> c<52> l<9:16> el<9:19>
n<> u<54> t<Constant_mintypmax_expression> p<55> c<53> l<9:16> el<9:19>
n<> u<55> t<Constant_param_expression> p<56> c<54> l<9:16> el<9:19>
n<> u<56> t<Param_assignment> p<57> c<49> l<9:13> el<9:19>
n<> u<57> t<List_of_param_assignments> p<58> c<56> l<9:13> el<9:19>
n<> u<58> t<Parameter_declaration> p<59> c<48> l<9:3> el<9:19>
n<> u<59> t<Package_or_generate_item_declaration> p<60> c<58> l<9:3> el<9:20>
n<> u<60> t<Module_or_generate_item_declaration> p<61> c<59> l<9:3> el<9:20>
n<> u<61> t<Module_common_item> p<62> c<60> l<9:3> el<9:20>
n<> u<62> t<Module_or_generate_item> p<63> c<61> l<9:3> el<9:20>
n<> u<63> t<Non_port_module_item> p<64> c<62> l<9:3> el<9:20>
n<> u<64> t<Module_item> p<66> c<63> s<65> l<9:3> el<9:20>
n<> u<65> t<ENDMODULE> p<66> l<11:1> el<11:10>
n<> u<66> t<Module_declaration> p<67> c<47> l<7:1> el<11:10>
n<> u<67> t<Description> p<68> c<66> l<7:1> el<11:10>
n<> u<68> t<Source_text> p<69> c<15> l<1:1> el<11:10>
n<> u<69> t<Top_level_rule> c<1> l<1:1> el<11:10>
n<GOOD> u<44> t<StringConst> p<47> s<46> l<7:8> el<7:12>
n<> u<45> t<Port> p<46> l<7:13> el<7:13>
n<> u<46> t<List_of_ports> p<47> c<45> l<7:12> el<7:14>
n<> u<47> t<Module_nonansi_header> p<49> c<43> s<48> l<7:1> el<7:15>
n<> u<48> t<ENDMODULE> p<49> l<9:1> el<9:10>
n<> u<49> t<Module_declaration> p<50> c<47> l<7:1> el<9:10>
n<> u<50> t<Description> p<105> c<49> s<104> l<7:1> el<9:10>
n<module> u<51> t<Module_keyword> p<55> s<52> l<11:1> el<11:7>
n<top> u<52> t<StringConst> p<55> s<54> l<11:8> el<11:11>
n<> u<53> t<Port> p<54> l<11:12> el<11:12>
n<> u<54> t<List_of_ports> p<55> c<53> l<11:11> el<11:13>
n<> u<55> t<Module_nonansi_header> p<103> c<51> s<72> l<11:1> el<11:14>
n<> u<56> t<Data_type_or_implicit> p<66> s<65> l<13:13> el<13:13>
n<D> u<57> t<StringConst> p<64> s<63> l<13:13> el<13:14>
n<MAP> u<58> t<StringConst> p<59> l<13:16> el<13:19>
n<> u<59> t<Primary_literal> p<60> c<58> l<13:16> el<13:19>
n<> u<60> t<Constant_primary> p<61> c<59> l<13:16> el<13:19>
n<> u<61> t<Constant_expression> p<62> c<60> l<13:16> el<13:19>
n<> u<62> t<Constant_mintypmax_expression> p<63> c<61> l<13:16> el<13:19>
n<> u<63> t<Constant_param_expression> p<64> c<62> l<13:16> el<13:19>
n<> u<64> t<Param_assignment> p<65> c<57> l<13:13> el<13:19>
n<> u<65> t<List_of_param_assignments> p<66> c<64> l<13:13> el<13:19>
n<> u<66> t<Parameter_declaration> p<67> c<56> l<13:3> el<13:19>
n<> u<67> t<Package_or_generate_item_declaration> p<68> c<66> l<13:3> el<13:20>
n<> u<68> t<Module_or_generate_item_declaration> p<69> c<67> l<13:3> el<13:20>
n<> u<69> t<Module_common_item> p<70> c<68> l<13:3> el<13:20>
n<> u<70> t<Module_or_generate_item> p<71> c<69> l<13:3> el<13:20>
n<> u<71> t<Non_port_module_item> p<72> c<70> l<13:3> el<13:20>
n<> u<72> t<Module_item> p<103> c<71> s<101> l<13:3> el<13:20>
n<D> u<73> t<StringConst> p<74> l<15:7> el<15:8>
n<> u<74> t<Primary_literal> p<75> c<73> l<15:7> el<15:8>
n<> u<75> t<Constant_primary> p<76> c<74> l<15:7> el<15:8>
n<> u<76> t<Constant_expression> p<82> c<75> s<81> l<15:7> el<15:8>
n<17'b00000000000000000000000000010000> u<77> t<IntConst> p<78> l<15:12> el<15:48>
n<> u<78> t<Primary_literal> p<79> c<77> l<15:12> el<15:48>
n<> u<79> t<Constant_primary> p<80> c<78> l<15:12> el<15:48>
n<> u<80> t<Constant_expression> p<82> c<79> l<15:12> el<15:48>
n<> u<81> t<BinOp_Equiv> p<82> s<80> l<15:9> el<15:11>
n<> u<82> t<Constant_expression> p<96> c<76> s<94> l<15:7> el<15:48>
n<GOOD> u<83> t<StringConst> p<89> s<88> l<16:6> el<16:10>
n<good> u<84> t<StringConst> p<85> l<16:11> el<16:15>
n<> u<85> t<Name_of_instance> p<88> c<84> s<87> l<16:11> el<16:15>
n<> u<86> t<Ordered_port_connection> p<87> l<16:16> el<16:16>
n<> u<87> t<List_of_port_connections> p<88> c<86> l<16:16> el<16:16>
n<> u<88> t<Hierarchical_instance> p<89> c<85> l<16:11> el<16:17>
n<> u<89> t<Module_instantiation> p<90> c<83> l<16:6> el<16:18>
n<> u<90> t<Module_or_generate_item> p<91> c<89> l<16:6> el<16:18>
n<> u<91> t<Generate_item> p<93> c<90> s<92> l<16:6> el<16:18>
n<> u<92> t<END> p<93> l<17:3> el<17:6>
n<> u<93> t<Generate_begin_end_block> p<94> c<91> l<15:50> el<17:6>
n<> u<94> t<Generate_item> p<96> c<93> l<15:50> el<17:6>
n<> u<95> t<IF> p<96> s<82> l<15:3> el<15:5>
n<> u<96> t<If_generate_construct> p<97> c<95> l<15:3> el<17:6>
n<> u<97> t<Conditional_generate_construct> p<98> c<96> l<15:3> el<17:6>
n<> u<98> t<Module_common_item> p<99> c<97> l<15:3> el<17:6>
n<> u<99> t<Module_or_generate_item> p<100> c<98> l<15:3> el<17:6>
n<> u<100> t<Non_port_module_item> p<101> c<99> l<15:3> el<17:6>
n<> u<101> t<Module_item> p<103> c<100> s<102> l<15:3> el<17:6>
n<> u<102> t<ENDMODULE> p<103> l<19:1> el<19:10>
n<> u<103> t<Module_declaration> p<104> c<55> l<11:1> el<19:10>
n<> u<104> t<Description> p<105> c<103> l<11:1> el<19:10>
n<> u<105> t<Source_text> p<106> c<15> l<1:1> el<19:10>
n<> u<106> t<Top_level_rule> c<1> l<1:1> el<20:1>
AST_DEBUG_END
[WRN:PA0205] ${SURELOG_DIR}/tests/FileLocalParam/dut.sv:7:1: No timescale set for "top".
[INF:CP0300] Compilation...
[INF:CP0303] ${SURELOG_DIR}/tests/FileLocalParam/dut.sv:7:1: Compile module "work@top".
[INF:CP0303] ${SURELOG_DIR}/tests/FileLocalParam/dut.sv:7:1: Compile module "work@GOOD".
[INF:CP0303] ${SURELOG_DIR}/tests/FileLocalParam/dut.sv:11:1: Compile module "work@top".
[INF:EL0526] Design Elaboration...
[NTE:EL0503] ${SURELOG_DIR}/tests/FileLocalParam/dut.sv:7:1: Top level module "work@top".
[INF:CP0335] ${SURELOG_DIR}/tests/FileLocalParam/dut.sv:16:6: Compile generate block "work@top.genblk1".
[NTE:EL0503] ${SURELOG_DIR}/tests/FileLocalParam/dut.sv:11:1: Top level module "work@top".
[NTE:EL0508] Nb Top level modules: 1.
[NTE:EL0509] Max instance depth: 1.
[NTE:EL0510] Nb instances: 1.
[NTE:EL0509] Max instance depth: 3.
[NTE:EL0510] Nb instances: 2.
[NTE:EL0511] Nb leaf instances: 1.
[INF:UH0706] Creating UHDM Model...
=== UHDM Object Stats Begin (Non-Elaborated Model) ===
constant 7
begin 1
constant 17
design 1
int_typespec 5
module_inst 5
operation 3
gen_if 1
gen_scope 2
gen_scope_array 2
int_typespec 7
module_inst 6
operation 5
param_assign 6
parameter 6
range 2
ref_obj 6
ref_typespec 8
ref_module 2
ref_obj 4
ref_typespec 11
=== UHDM Object Stats End ===
[INF:UH0707] Elaborating UHDM...
=== UHDM Object Stats Begin (Elaborated Model) ===
constant 7
begin 1
constant 17
design 1
int_typespec 5
module_inst 5
operation 3
gen_if 1
gen_scope 3
gen_scope_array 3
int_typespec 7
module_inst 7
operation 5
param_assign 6
parameter 6
range 2
ref_obj 6
ref_typespec 8
ref_module 2
ref_obj 4
ref_typespec 11
=== UHDM Object Stats End ===
[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/FileLocalParam/slpp_all/surelog.uhdm ...
[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/FileLocalParam/slpp_all/checker/surelog.chk.html ...
Expand All @@ -117,31 +165,71 @@ design: (work@top)
|vpiElaborated:1
|vpiName:work@top
|uhdmallModules:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:7:1, endln:11:10
\_module_inst: work@GOOD (work@GOOD), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:7:1, endln:9:10
|vpiParent:
\_design: (work@top)
|vpiFullName:work@GOOD
|vpiDefName:work@GOOD
|uhdmallModules:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:11:1, endln:19:10
|vpiParent:
\_design: (work@top)
|vpiFullName:work@top
|vpiParameter:
\_parameter: (work@top.D), line:9:13, endln:9:14
\_parameter: (work@top.D), line:13:13, endln:13:14
|vpiParent:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:7:1, endln:11:10
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:11:1, endln:19:10
|vpiName:D
|vpiFullName:work@top.D
|vpiParamAssign:
\_param_assign: , line:9:13, endln:9:19
\_param_assign: , line:13:13, endln:13:19
|vpiParent:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:7:1, endln:11:10
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:11:1, endln:19:10
|vpiRhs:
\_ref_obj: (work@top.MAP), line:9:16, endln:9:19
\_ref_obj: (work@top.MAP), line:13:16, endln:13:19
|vpiParent:
\_param_assign: , line:9:13, endln:9:19
\_param_assign: , line:13:13, endln:13:19
|vpiName:MAP
|vpiFullName:work@top.MAP
|vpiActual:
\_parameter: (MAP), line:3:23, endln:3:26
|vpiLhs:
\_parameter: (work@top.D), line:9:13, endln:9:14
\_parameter: (work@top.D), line:13:13, endln:13:14
|vpiDefName:work@top
|vpiGenStmt:
\_gen_if: , line:15:3, endln:15:5
|vpiParent:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:11:1, endln:19:10
|vpiCondition:
\_operation: , line:15:7, endln:15:48
|vpiParent:
\_gen_if: , line:15:3, endln:15:5
|vpiOpType:14
|vpiOperand:
\_ref_obj: (work@top.D), line:15:7, endln:15:8
|vpiParent:
\_operation: , line:15:7, endln:15:48
|vpiName:D
|vpiFullName:work@top.D
|vpiOperand:
\_constant: , line:15:12, endln:15:48
|vpiParent:
\_operation: , line:15:7, endln:15:48
|vpiDecompile:17'b00000000000000000000000000010000
|vpiSize:17
|BIN:00000000000000000000000000010000
|vpiConstType:3
|vpiStmt:
\_begin: (work@top)
|vpiParent:
\_gen_if: , line:15:3, endln:15:5
|vpiFullName:work@top
|vpiStmt:
\_ref_module: work@GOOD (good), line:16:11, endln:16:15
|vpiParent:
\_begin: (work@top)
|vpiName:good
|vpiDefName:work@GOOD
|vpiParameter:
\_parameter: (AWIDTH), line:1:25, endln:1:31
|vpiParent:
Expand All @@ -160,6 +248,7 @@ design: (work@top)
\_parameter: (MAP), line:3:23, endln:3:26
|vpiParent:
\_design: (work@top)
|BIN:00000000000000000000000000010000
|vpiTypespec:
\_ref_typespec: (MAP)
|vpiParent:
Expand Down Expand Up @@ -194,43 +283,66 @@ design: (work@top)
|vpiParent:
\_design: (work@top)
|vpiRhs:
\_operation: , line:3:33, endln:5:48
\_constant: , line:3:33, endln:5:48
|vpiParent:
\_param_assign: , line:3:23, endln:5:48
|vpiOpType:33
|vpiOperand:
\_ref_obj: (AWIDTH), line:4:3, endln:4:9
|vpiSize:17
|BIN:00000000000000000000000000010000
|vpiTypespec:
\_ref_typespec:
|vpiParent:
\_operation: , line:3:33, endln:5:48
|vpiName:AWIDTH
\_constant: , line:3:33, endln:5:48
|vpiActual:
\_int_typespec: , line:3:12, endln:3:22
|vpiConstType:3
|vpiLhs:
\_parameter: (MAP), line:3:23, endln:3:26
|uhdmtopModules:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:7:1, endln:11:10
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:11:1, endln:19:10
|vpiName:work@top
|vpiParameter:
\_parameter: (work@top.D), line:9:13, endln:9:14
\_parameter: (work@top.D), line:13:13, endln:13:14
|vpiParent:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:7:1, endln:11:10
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:11:1, endln:19:10
|vpiName:D
|vpiFullName:work@top.D
|vpiParamAssign:
\_param_assign: , line:9:13, endln:9:19
\_param_assign: , line:13:13, endln:13:19
|vpiParent:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:7:1, endln:11:10
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:11:1, endln:19:10
|vpiRhs:
\_ref_obj: (work@top.MAP), line:9:16, endln:9:19
\_constant: , line:13:16, endln:13:19
|vpiParent:
\_param_assign: , line:9:13, endln:9:19
|vpiName:MAP
|vpiFullName:work@top.MAP
|vpiActual:
\_parameter: (MAP), line:3:23, endln:3:26
\_param_assign: , line:13:13, endln:13:19
|vpiDecompile:17'b00000000000000000000000000010000
|vpiSize:17
|BIN:00000000000000000000000000010000
|vpiConstType:3
|vpiLhs:
\_parameter: (work@top.D), line:9:13, endln:9:14
\_parameter: (work@top.D), line:13:13, endln:13:14
|vpiDefName:work@top
|vpiTop:1
|vpiTopModule:1
|vpiGenScopeArray:
\_gen_scope_array: (work@top.genblk1), line:16:6, endln:16:18
|vpiParent:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:11:1, endln:19:10
|vpiName:genblk1
|vpiFullName:work@top.genblk1
|vpiGenScope:
\_gen_scope: (work@top.genblk1), line:16:6, endln:16:18
|vpiParent:
\_gen_scope_array: (work@top.genblk1), line:16:6, endln:16:18
|vpiFullName:work@top.genblk1
|vpiModule:
\_module_inst: work@GOOD (work@top.genblk1.good), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:16:6, endln:16:18
|vpiParent:
\_gen_scope: (work@top.genblk1), line:16:6, endln:16:18
|vpiName:good
|vpiFullName:work@top.genblk1.good
|vpiDefName:work@GOOD
|vpiDefFile:${SURELOG_DIR}/tests/FileLocalParam/dut.sv
|vpiDefLineNo:7
\_weaklyReferenced:
\_int_typespec: , line:1:1, endln:1:58
\_int_typespec: , line:3:12, endln:3:22
Expand Down Expand Up @@ -270,5 +382,5 @@ design: (work@top)
[ FATAL] : 0
[ SYNTAX] : 0
[ ERROR] : 0
[WARNING] : 1
[WARNING] : 0
[ NOTE] : 5
2 changes: 1 addition & 1 deletion tests/FileLocalParam/FileLocalParam.sl
View file
@@ -1 +1 @@
-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin
-parse -d uhdm -d coveruhdm -synth -elabuhdm -d ast dut.sv -nobuiltin
10 changes: 9 additions & 1 deletion tests/FileLocalParam/dut.sv
View file
Expand Up @@ -4,8 +4,16 @@ localparam [AWIDTH:0] MAP ={
AWIDTH
};

module GOOD();

endmodule

module top();

parameter D =MAP;

endmodule
if (D == 17'b00000000000000000000000000010000) begin
GOOD good();
end

endmodule

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