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Add riscvassembler lib to community projects (#3717)
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carlosedp committed Jan 8, 2024
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Expand Up @@ -28,33 +28,34 @@ If you want to add your project to the list, let us know on the [Chisel users ma

### Chisel

| Project | Description | Author | Links |
|----------------------------------------------------------------------------------------------------------------------------------------------|-----------------------------------------------------------------|----------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------|
| [Rocket Chip Generator](https://github.com/chipsalliance/rocket-chip) | RISC-V System-on-Chip Generator, 5-stage RISC-V Microprocessor | [`@ucb-bar`](https://github.com/ucb-bar), [`@sifive`](https://github.com/sifive) | [Report](https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html) |
| [Berkeley Out-of-order Machine](https://github.com/ucb-bar/riscv-boom) | RISC-V Out-of-order/Multi-issue Microprocessor | [`@ucb-bar`](https://github.com/ucb-bar) | [Site](https://boom-core.org/), [Thesis](http://www2.eecs.berkeley.edu/Pubs/TechRpts/2018/EECS-2018-151.pdf) |
| [RISC-V Mini](https://github.com/ucb-bar/riscv-mini) | 3-stage RISC-V Microprocessor | [`@ucb-bar`](https://github.com/ucb-bar) | |
| [Sodor Processor Collection](https://github.com/ucb-bar/riscv-sodor) | Educational RISC-V Microprocessors (1, 2, 3, 5-stage) | [`@ucb-bar`](https://github.com/ucb-bar) | |
| [Patmos](https://github.com/t-crest/patmos) | Time-predictable VLIW processor | [`@t-crest`](https://github.com/t-crest) | [Site](http://patmos.compute.dtu.dk/) |
| [OpenSoC Fabric](https://github.com/LBL-CoDEx/OpenSoCFabric) | Parametrizable Network-on-Chip Generator | [`@LBL-CoDEx`](https://github.com/LBL-CoDEx) | [Site](http://www.opensocfabric.org) |
| [Hwacha](https://github.com/ucb-bar/hwacha) | Decoupled Vector-fetch Accelerator | [`@ucb-bar`](https://github.com/ucb-bar) | [Report](https://people.eecs.berkeley.edu/~krste/papers/EECS-2015-263.pdf) |
| [DANA](https://github.com/bu-icsg/dana) | Multilayer Perceptron Accelerator for Rocket | [`@bu-icsg`](https://github.com/bu-icsg) | [Paper](http://people.bu.edu/schuye/files/pact2015-eldridge-paper.pdf) |
| [Gemmini](https://github.com/ucb-bar/gemmini) | Systolic-array Accelerator Generator | [`@ucb-bar`](https://github.com/ucb-bar) | [Paper](https://arxiv.org/pdf/1911.09925) |
| [Edge TPU](https://cloud.google.com/edge-tpu) | AI Inference Accelerator | [`@google`](https://github.com/google) | [Video](https://www.youtube.com/watch?v=x85342Cny8c) |
| [ChiselFlow](https://github.com/apl-cornell/ChiselFlow) | Information Flow Types in Chisel3 | [`@apl-cornell`](https://github.com/apl-cornell) | [Paper](https://ecommons.cornell.edu/xmlui/bitstream/handle/1813/57673/paper.pdf) |
| [PHMon](https://github.com/bu-icsg/PHMon/tree/code) | Programmable Hardware Monitor | [`@bu-icsg`](https://github.com/bu-icsg) | [Paper](http://people.bu.edu/joshi/files/sec20spring_delshadtehrani_prepub.pdf) |
| [DINO CPU](https://github.com/jlpteaching/dinocpu) | Davis In-Order (DINO) CPU models | [`@jlpteaching`](https://github.com/jlpteaching) | [Paper](https://dl.acm.org/doi/10.1145/3338698.3338892) |
| [Quasar](https://github.com/Lampro-Mellon/Quasar) | CHISEL implementation of SweRV-EL2 | [`@Lampro-Mellon`](https://github.com/Lampro-Mellon) | [Video](https://www.youtube.com/watch?v=R9eCNmGa5Vc) |
| FP Divider [Pipelined](https://github.com/Ssavas/fp-division-pipelined) / [Not Pipelined](https://github.com/Ssavas/fp-division-no-pipeline) | IEEE binary 32-bit divider using Harmonized Parabolic Synthesis | [`@Ssavas`](https://github.com/Ssavas) | [Paper](https://ieeexplore.ieee.org/abstract/document/7987504) |
| Square Root [Pipelined](https://github.com/Ssavas/sqrt-pipelined) / [Not Pipelined](https://github.com/Ssavas/sqrt-no-pipeline) | Square Root using Harmonized Parabolic Synthesis | [`@Ssavas`](https://github.com/Ssavas) | [Paper](http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-39322) |
| [Pillars](https://github.com/pku-dasys/pillars) | A Consistent CGRA Design Framework | [`@pku-dasys`](https://github.com/pku-dasys) | [Paper](https://woset-workshop.github.io/PDFs/2020/a22.pdf), [Video](https://www.youtube.com/watch?v=oNLyD6koB2g) |
| [Tensil](https://github.com/tensil-ai/tensil) | Machine Learning Accelerators | [`@tensil-ai`](https://github.com/tensil-ai) | [Website](https://www.tensil.ai) |
| [Twine](https://github.com/Twine-Umich/Twine) | A Chisel Extension for Component-Level Heterogeneous Design | [`@shibo-chen`](https://github.com/shibo-chen) | [Paper](https://drive.google.com/file/d/10tDsvv2CSC70GNb_KCFDwXHq4UHdTumm/view) |
| Project | Description | Author | Links |
| -------------------------------------------------------------------------------------------------------------------------------------------- | --------------------------------------------------------------- | -------------------------------------------------------------------------------- | ------------------------------------------------------------------------------------------------------------------ |
| [Rocket Chip Generator](https://github.com/chipsalliance/rocket-chip) | RISC-V System-on-Chip Generator, 5-stage RISC-V Microprocessor | [`@ucb-bar`](https://github.com/ucb-bar), [`@sifive`](https://github.com/sifive) | [Report](https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html) |
| [Berkeley Out-of-order Machine](https://github.com/ucb-bar/riscv-boom) | RISC-V Out-of-order/Multi-issue Microprocessor | [`@ucb-bar`](https://github.com/ucb-bar) | [Site](https://boom-core.org/), [Thesis](http://www2.eecs.berkeley.edu/Pubs/TechRpts/2018/EECS-2018-151.pdf) |
| [RISC-V Mini](https://github.com/ucb-bar/riscv-mini) | 3-stage RISC-V Microprocessor | [`@ucb-bar`](https://github.com/ucb-bar) | |
| [Sodor Processor Collection](https://github.com/ucb-bar/riscv-sodor) | Educational RISC-V Microprocessors (1, 2, 3, 5-stage) | [`@ucb-bar`](https://github.com/ucb-bar) | |
| [Patmos](https://github.com/t-crest/patmos) | Time-predictable VLIW processor | [`@t-crest`](https://github.com/t-crest) | [Site](http://patmos.compute.dtu.dk/) |
| [OpenSoC Fabric](https://github.com/LBL-CoDEx/OpenSoCFabric) | Parametrizable Network-on-Chip Generator | [`@LBL-CoDEx`](https://github.com/LBL-CoDEx) | [Site](http://www.opensocfabric.org) |
| [Hwacha](https://github.com/ucb-bar/hwacha) | Decoupled Vector-fetch Accelerator | [`@ucb-bar`](https://github.com/ucb-bar) | [Report](https://people.eecs.berkeley.edu/~krste/papers/EECS-2015-263.pdf) |
| [DANA](https://github.com/bu-icsg/dana) | Multilayer Perceptron Accelerator for Rocket | [`@bu-icsg`](https://github.com/bu-icsg) | [Paper](http://people.bu.edu/schuye/files/pact2015-eldridge-paper.pdf) |
| [Gemmini](https://github.com/ucb-bar/gemmini) | Systolic-array Accelerator Generator | [`@ucb-bar`](https://github.com/ucb-bar) | [Paper](https://arxiv.org/pdf/1911.09925) |
| [Edge TPU](https://cloud.google.com/edge-tpu) | AI Inference Accelerator | [`@google`](https://github.com/google) | [Video](https://www.youtube.com/watch?v=x85342Cny8c) |
| [ChiselFlow](https://github.com/apl-cornell/ChiselFlow) | Information Flow Types in Chisel3 | [`@apl-cornell`](https://github.com/apl-cornell) | [Paper](https://ecommons.cornell.edu/xmlui/bitstream/handle/1813/57673/paper.pdf) |
| [PHMon](https://github.com/bu-icsg/PHMon/tree/code) | Programmable Hardware Monitor | [`@bu-icsg`](https://github.com/bu-icsg) | [Paper](http://people.bu.edu/joshi/files/sec20spring_delshadtehrani_prepub.pdf) |
| [DINO CPU](https://github.com/jlpteaching/dinocpu) | Davis In-Order (DINO) CPU models | [`@jlpteaching`](https://github.com/jlpteaching) | [Paper](https://dl.acm.org/doi/10.1145/3338698.3338892) |
| [Quasar](https://github.com/Lampro-Mellon/Quasar) | CHISEL implementation of SweRV-EL2 | [`@Lampro-Mellon`](https://github.com/Lampro-Mellon) | [Video](https://www.youtube.com/watch?v=R9eCNmGa5Vc) |
| FP Divider [Pipelined](https://github.com/Ssavas/fp-division-pipelined) / [Not Pipelined](https://github.com/Ssavas/fp-division-no-pipeline) | IEEE binary 32-bit divider using Harmonized Parabolic Synthesis | [`@Ssavas`](https://github.com/Ssavas) | [Paper](https://ieeexplore.ieee.org/abstract/document/7987504) |
| Square Root [Pipelined](https://github.com/Ssavas/sqrt-pipelined) / [Not Pipelined](https://github.com/Ssavas/sqrt-no-pipeline) | Square Root using Harmonized Parabolic Synthesis | [`@Ssavas`](https://github.com/Ssavas) | [Paper](http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-39322) |
| [Pillars](https://github.com/pku-dasys/pillars) | A Consistent CGRA Design Framework | [`@pku-dasys`](https://github.com/pku-dasys) | [Paper](https://woset-workshop.github.io/PDFs/2020/a22.pdf), [Video](https://www.youtube.com/watch?v=oNLyD6koB2g) |
| [Tensil](https://github.com/tensil-ai/tensil) | Machine Learning Accelerators | [`@tensil-ai`](https://github.com/tensil-ai) | [Website](https://www.tensil.ai) |
| [Twine](https://github.com/Twine-Umich/Twine) | A Chisel Extension for Component-Level Heterogeneous Design | [`@shibo-chen`](https://github.com/shibo-chen) | [Paper](https://drive.google.com/file/d/10tDsvv2CSC70GNb_KCFDwXHq4UHdTumm/view) |
| [RISCVAssembler](https://github.com/carlosedp/riscvassembler) | A RISC-V assembler library for Scala/Chisel projects | [`@carlosedp`](https://github.com/carlosedp) | [Site](https://index.scala-lang.org/carlosedp/riscvassembler), [Demo Site](https://carlosedp.github.io/rvasmweb/)) |


### FIRRTL

| Project | Description | Author | Links |
|--------------------------------------------------------------------------------------------------------------|------------------------------------------|--------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| ------------------------------------------------------------------------------------------------------------ | ---------------------------------------- | ------------------------------------------------ | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
| [MIDAS/DESSERT/Golden Gate](https://github.com/ucb-bar/midas) | FPGA Accelerated Simulation | [`@ucb-bar`](https://github.com/ucb-bar) | Papers [1](https://people.eecs.berkeley.edu/~biancolin/papers/carrv17.pdf), [2](http://people.eecs.berkeley.edu/~biancolin/papers/dessert-fpl18.pdf), [3](https://davidbiancolin.github.io/papers/goldengate-iccad19.pdf), [Video](https://www.youtube.com/watch?v=Tvcd4u4_ELM) |
| [Chiffre](https://github.com/IBM/chiffre) | Run-time Fault Injection | [`@IBM`](https://github.com/IBM) | [Paper](https://carrv.github.io/2018/papers/CARRV_2018_paper_2.pdf) |
| [SIRRTL](https://github.com/apl-cornell/sirrtl) | Security-typed FIRRTL | [`@apl-cornell`](https://github.com/apl-cornell) | [Paper](https://ecommons.cornell.edu/xmlui/bitstream/handle/1813/57673/paper.pdf) |
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