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This repository has been archived by the owner on Aug 20, 2024. It is now read-only.

chipsalliance / firrtl Public archive

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architecture.05.05.15.txt

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Omar/Ofar? wrote genesis and is Dave's boss

Big problem is how to integrate different verilog, and put them all together to make it work

Can chisel help?

Different clock domains? L2 should be in a different domain

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