Merge pull request #61 from antmicro/add-sing-io-test

Added an OBUFT test

tests/features/CMakeLists.txt

@@ -1,6 +1,6 @@
 add_subdirectory(clock_gen)
 add_subdirectory(diff_io)
-add_subdirectory(iobuf)
+add_subdirectory(sing_io)
 add_subdirectory(lut)
 add_subdirectory(ram)
 add_subdirectory(ram_36bit)

tests/features/sing_io/CMakeLists.txt

@@ -0,0 +1,16 @@
+add_generic_test(
+    name iobuf
+    board_list basys3
+    constr_prefix iobuf
+    sources iobuf.v
+    testbench iobuf_tb.v
+)
+
+add_generic_test(
+    name obuft
+    board_list basys3
+    constr_prefix obuft
+    sources obuft.v
+    testbench obuft_tb.v
+)
+

tests/features/sing_io/obuft-basys3.xdc

@@ -0,0 +1,7 @@
+set_property PACKAGE_PIN V17 [get_ports sw[0]]
+set_property PACKAGE_PIN V16 [get_ports sw[1]]
+set_property PACKAGE_PIN K17 [get_ports jc1]
+
+set_property IOSTANDARD LVCMOS33 [get_ports sw[0]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[1]]
+set_property IOSTANDARD LVCMOS33 [get_ports jc1]

tests/features/sing_io/obuft.v

@@ -0,0 +1,37 @@
+// Copyright (C) 2021  The Symbiflow Authors.
+//
+// Use of this source code is governed by a ISC-style
+// license that can be found in the LICENSE file or at
+// https://opensource.org/licenses/ISC
+//
+// SPDX-License-Identifier: ISC
+
+// Truth table:
+//
+// SW1 SW0 | jc1
+//  0   0  |  0
+//  0   1  |  1
+//  1   0  |  z
+//  1   1  |  z
+
+module top (
+    input   wire [1:0] sw,
+    inout   wire jc1
+);
+
+wire io_i;
+wire io_t;
+
+OBUFT obuft
+(
+    .I  (io_i),
+    .T  (io_t),
+    .O  (jc1)
+);
+
+// SW0 controls OBUFT.I
+assign io_i = sw[0];
+// SW1 controls OBUFT.T
+assign io_t = sw[1];
+
+endmodule

tests/features/sing_io/obuft_tb.v

@@ -0,0 +1,53 @@
+// Copyright (C) 2021  The Symbiflow Authors.
+//
+// Use of this source code is governed by a ISC-style
+// license that can be found in the LICENSE file or at
+// https://opensource.org/licenses/ISC
+//
+// SPDX-License-Identifier: ISC
+
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+module tb;
+
+`include "utils.v"
+
+reg clk;
+reg rst;
+
+reg [1:0] sw;
+
+always #5 clk <= !clk;
+
+initial begin
+    clk = 1'b0;
+    rst = 1'b1;
+    sw  = 2'b0;
+
+    #10 rst = 1'b0;
+
+    $dumpfile(`STRINGIFY(`VCD));
+    $dumpvars;
+    #100 $finish();
+end
+
+wire jc1;
+
+top dut(
+    .sw(sw),
+    .jc1(jc1)
+);
+
+always @(posedge clk) begin
+    if (rst)
+        sw <= 0;
+    else
+        sw <= sw + 1;
+
+    assert(sw[1] != 1  || jc1 === 1'bz, sw);
+    assert(sw != 2'b00 || jc1 === 1'b0, sw);
+    assert(sw != 2'b01 || jc1 === 1'b1, sw);
+end
+
+endmodule