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Enable baselitex on nexys video #257

Merged
merged 4 commits into from
Dec 14, 2020
Merged

Enable baselitex on nexys video #257

merged 4 commits into from
Dec 14, 2020

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wtatarski
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@mithro mithro requested a review from HackerFoo October 28, 2020 18:41
@wtatarski wtatarski force-pushed the enable-baselitex-nexys-video branch 3 times, most recently from c26dd61 to 46bd53d Compare October 29, 2020 17:06
@wtatarski wtatarski force-pushed the enable-baselitex-nexys-video branch 3 times, most recently from ef153c6 to ab524df Compare November 3, 2020 15:49
@mithro mithro mentioned this pull request Nov 3, 2020
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acomodi commented Nov 23, 2020

@mithro @HackerFoo I have generated a new design with VexRiscV_Linux.

This was achieved with f4pga/f4pga-arch-defs#1797 to land and the current symbiflow install packges uses the #1797 artifacts.

The design works at 100MHz, as a lower frequency does not work (even with Vivado), as the DDR memtest fails.

There is also an issue with the IDELAYCTRL, which I needed to temporary workaround.
Basically, the litex design contains now two banks of IDELAYs, one for ethernet and one for DDR. The problem is that there is only one instance of IDELAYCTRL which gets replicated by Vivado and not by Symbiflow, causing an issue during placement constraints generation. I will open an issue about this on symbiflow-arch-defs.

The bitstream is able to load Linux, but there seem to be problems with ethernet, as the loading process does not properly work and, once booted with lxterm, pinging the host at 192.168.1.100 produces no effect.

@HackerFoo HackerFoo added this to Blocking in Litex w/Linux on 200T Nov 24, 2020
@HackerFoo HackerFoo moved this from Blocking to In Progress in Litex w/Linux on 200T Nov 24, 2020
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acomodi commented Nov 27, 2020

@HackerFoo @mithro I got the ethernet working, as a result of fixing IDDR and ODDR primitives in fasm2bels: chipsalliance/f4pga-xc-fasm2bels#36

To get this merged and tested we need to merge the following PRs:

  • Yosys-Plugins SDC fix: This will require an update in symbiflow-arch-defs as well. This solves the issue for which we are getting inexistent clocks in the SDC
  • IDDR/ODDR fix

With these fixes Linux can boot from ethernet successfully.

@acomodi acomodi force-pushed the enable-baselitex-nexys-video branch from 871af42 to 6f707bc Compare December 9, 2020 15:16
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acomodi commented Dec 9, 2020

@HackerFoo I have updated the test sources and applied some fixes to have the baselitex design working for 200T:

  1. SDC plugin does not output the BUFG out clocks anymore yosys-f4pga-plugins#64 This issue causes to have some missing clock constraints which result in VPR to not optimize the CP during P&R. To overcome this I have transitioned to use the manual SDC file. Once the issue is fixed and the package updated in archdefs, we can go back at having the XDC constraints only.

  2. LOC constraints on the PLLs: Artix 200T missing bits f4pga/f4pga-arch-defs#1750

  3. Duplication of the IDELAYCTRL: Auto-infer IDELACTRL if there are more IDELAY banks used f4pga/f4pga-arch-defs#1804

With these workarounds, the design builds successfully, at least locally.

@acomodi
Add linux-litex for nexys-video
a5a0c30 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Wojciech Tatarski <wtatarski@antmicro.com>
@acomodi
baselitex-nexys-video: use SDC for clocks
307016f 
See issue:
chipsalliance/yosys-f4pga-plugins#64

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
@acomodi
env: update environment to use litex-hub
30578a1 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
@acomodi
baselitex nexys video: remove nextpnr and yosys-vivado for FD retarget
cecac53 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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acomodi commented Dec 10, 2020 •
edited

@HackerFoo There is an outstanding issue with the ODDR preventing ethernet to work on HW with the current status of this PR (the design can still be placed and routed though). Fix is here in arch-defs f4pga/f4pga-arch-defs#1870 (review).

With that fix in, ethernet works fine, and Linux boots

HackerFoo
HackerFoo reviewed Dec 12, 2020
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conf/symbiflow/environment.yml
- litex-hub::symbiflow-yosys-plugins=1.0.0_7_g59ff1e6_23_g3a95697_17_g00b887b_0194_g40efa51=20201120_145821
- litex-hub::prjxray-tools=0.1_2697_g0f939808=20201120_145821
- litex-hub::prjxray-db=0.0_0239_gd87c844=20201120_145821
- litex-hub::vtr=v8.0.0_3011_gb0223dc59=20201202_112618
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Is this supposed to be synchronized with symbiflow-arch-defs somehow? This is not the same as the version used by symbiflow-arch-defs (currently d912bdb88)

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Currently, in CI we are using the environment.yml coming from the symbiflow-arch-defs install package, and not this one. I am unsure how to deal with the update of this static environment.yml, for now it needs to be manual.

To override which environment variable to use (at least when building in conda) you can do:

ENVIRONMENT_FILE=<custom_env> make env

the default points at the one in conf/symbiflow/environment.yml.

@acomodi acomodi merged commit c41755e into chipsalliance:master Dec 14, 2020
@litghost litghost moved this from In Progress to Fixed in Litex w/Linux on 200T Dec 16, 2020
@kgugala kgugala removed this from Fixed in Litex w/Linux on 200T Jan 17, 2022
@umarcor umarcor deleted the enable-baselitex-nexys-video branch April 21, 2022 17:28
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@wtatarski @acomodi @HackerFoo @symbiflow-kokoro