Initial FASM generator

fpga_interchange/chip_info_utils.py

@@ -0,0 +1,31 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2021  The SymbiFlow Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+
+class LutCell():
+    def __init__(self):
+        self.name = ''
+        self.pins = []
+
+
+class LutBel():
+    def __init__(self):
+        self.name = ''
+        self.pins = []
+        self.low_bit = 0
+        self.high_bit = 0
+        self.out_pin = ''
+
+
+class LutElement():
+    def __init__(self):
+        self.width = 0
+        self.lut_bels = []

fpga_interchange/constraints/tool.py

@@ -27,7 +27,7 @@ def make_problem_from_device(device, allowed_sites):
     placement_oracle.add_sites_from_device(device)
 
     placements = []
-    for tile, site, tile_type, site_type, bel in device.yield_bels():
+    for tile, site, tile_type, site_type, bel, bel_type in device.yield_bels():
         if site not in allowed_sites:
             continue
 

fpga_interchange/device_resources.py

@@ -724,6 +724,16 @@ def get_tile_type(self, tile_type_index):
 
         return self.tile_types[tile_type_index]
 
+    def get_tile_name_at_site_name(self, site_name):
+        """ Get Tile name at site name. """
+        assert site_name in self.site_name_to_site
+        sites_dict = self.site_name_to_site[site_name]
+
+        # Get the first site in the dict. Assume all alternative sites are at
+        # the same tile
+        site = list(sites_dict.values())[0]
+        return self.strs[site.tile_name_index]
+
     def bel_pin(self, site_name, site_type, bel, pin):
         """ Return BelPin device resource for BEL pin in site.
 
@@ -881,7 +891,7 @@ def yield_bels(self):
 
                     for bel in site_type.bels:
                         yield tile_name, site_name, tile.tile_type, \
-                                site.site_type_name, bel.name
+                                site.site_type_name, bel.name, bel.type
 
     def get_primitive_library(self):
         from fpga_interchange.interchange_capnp import to_logical_netlist

fpga_interchange/fasm_generator.py

@@ -0,0 +1,44 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2021  The SymbiFlow Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+import argparse
+
+from fpga_interchange.interchange_capnp import Interchange
+from fpga_interchange.fasm_generators.xc7 import XC7FasmGenerator
+
+
+def main():
+    parser = argparse.ArgumentParser(description=__doc__)
+
+    parser.add_argument('--schema_dir', required=True)
+    parser.add_argument('--family', default='xc7')
+    parser.add_argument('device_resources')
+    parser.add_argument('logical_netlist')
+    parser.add_argument('physical_netlist')
+
+    args = parser.parse_args()
+
+    interchange = Interchange(args.schema_dir)
+
+    family_map = {
+        "xc7": XC7FasmGenerator,
+    }
+
+    device_resources = args.device_resources
+    logical_net = args.logical_netlist
+    physical_net = args.physical_netlist
+
+    fasm_generator = family_map[args.family](interchange, device_resources,
+                                             logical_net, physical_net)
+    fasm_generator.output_fasm()
+
+
+if __name__ == "__main__":
+    main()