Python code for generating and writing test architecture #85

mkurc-ant · 2021-05-19T14:53:23Z

This is a very WIP code that in the end should allow to easily define a test FPGA architecture with timings. Currently it generates and writes site types and tile types, no alternative site types supported.

gatecat · 2021-05-19T15:01:41Z

fpga_interchange/testarch_generators/device_resources_builder.py

+        self.bels[bel.name] = bel
+
+        # Add BEL pin
+        bel.add_pin(name, direction) # FIXME: Opposite direction ?!?!?!


Yeah - an input to the site from the tile is an output from the site port bel pin within the tile (think of it a bit like a 'buffer' that brings the signal into the tile)

Allright, thanks.

mtdudek · 2021-06-09T08:21:15Z

Testarch generated right now can be combined with gen_device_config.yaml in nextpnr_emit to emit testarch database, but when trying to run wire test, nextpnr fails on assertion in line 150 in arch_pack_io.cc

mtdudek · 2021-06-09T08:58:08Z

fpga_interchange/testarch_generators/generate_testarch.py


        w = site_type.add_wire("MUX_O")
        w.connect_to_bel_pin("FFMUX", "O")
        w.connect_to_bel_pin("FF", "D")

-        w = site_type.add_wire("LUT_OUT", [("LUT", "O"), ("O", "O")])


I had to remove wire "LUT_OUT" as there cannot be 2 wires driven by the same output.
This caused nextpnr_emit to fail

Yeah, this looks like a typo in any case as the O site pin is being correctly driven by the LUT_O wire anyway: https://github.com/antmicro/python-fpga-interchange/blob/399355e63c3edf9202ca373d371cfa7d1bfa92a4/fpga_interchange/testarch_generators/generate_testarch.py#L82

mtdudek · 2021-06-09T09:00:14Z

fpga_interchange/testarch_generators/generate_testarch.py

                is_perimeter = y in [0, self.grid_size[1] - 1] or \
                               x in [0, self.grid_size[0] - 1]
+                is_centre = y == self.grid_size[1] // 2 and x == self.grid_size[0] // 2


Nextpnr_emit expects tile 0,0 to be dummy/null tile.
Also nextpnr_emmit needs some way to inject GND and VCC signals, this is now done by PWR tile

Yeah, this is fair for now - eventually we do want to find a better solution to that

mtdudek · 2021-06-14T18:02:51Z

So far this works, testarch capnp is generated and is valid, I'm able to compile it to chip database, and with custom yosys techmaps and flow testarch can pass wire test, but const_wire is still not working.

gatecat · 2021-06-15T14:47:27Z

fpga_interchange/add_prim_lib.py

-        top_instance_name=None,
-        top_instance=None,
-        libraries=libraries)
+    netlist = LogicalNetlist(name=args.library,


Is there a reason for what appear to be just format changes in existing code that should have been auto-formatted already?

acomodi

A few comments in

.github/workflows/testarch_device.sh

.github/workflows/ci.yml

fpga_interchange/fasm_generators/xc7.py

fpga_interchange/populate_chip_info.py

.github/workflows/testarch_device.sh

acomodi

LGTM

gatecat · 2021-06-18T10:20:21Z

fpga_interchange/converters.py

@@ -434,7 +437,8 @@ def from_reader(message,
            continue

        if field_proto_data.ref_annotation is not None:
-            reference_fun = lambda value: reader.reference_value(field_proto_data.ref_annotation, value, root, parent)
+            reference_fun = lambda value: reader.reference_value(


I'm still slightly confused by these autoformatting changes, but it' passing CI so presumably this format is OK too?

gatecat · 2021-06-18T10:20:45Z

fpga_interchange/fasm_generators/xc7.py

-            features=["IN_USE", "ZINV_CE"],
-            callback=lambda m: "BUFHCE.BUFHCE_X{}Y{}".format(0 if m.group(1) == "L" else 1, m.group(2))
-            ))
+        site_thru_features.append(


Again, this seems to be just a formatting change unrelated to testarch?

gatecat · 2021-06-18T10:23:09Z

fpga_interchange/testarch_generators/generate_testarch.py

+        bel_ib.add_pin("I", Direction.Output)
+        bel_ib.add_pin("P", Direction.Input)
+
+        bel_ipad = site_type.add_bel("IPAD", "IPAD", BelCategory.LOGIC)


Not critical for now, but more realistic longer term would be to have one PAD bel like Xilinx rather than seperate IPAD and OPAD bels. This would be useful for testing bidirectional IO away from the complexity of real Xilinx IOBs.

Agreed, for now, a TODO comment to not lose track of this might be enough.

acomodi · 2021-06-21T10:39:02Z

This requires a rebase, and I think we can go ahead and merge once CI is green

Signed-off-by: Maciej Kurc <mkurc@antmicro.com> Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

Add dummy tile on 0,0 location in generate_testarch as populate_chip needs this tile to be empty Add gen_device_config.yaml for testarch Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

Fix primitives names to use global names Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

Const wire now passes Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

mkurc-ant marked this pull request as draft May 19, 2021 14:53

gatecat reviewed May 19, 2021

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mkurc-ant force-pushed the testarch-writer branch 4 times, most recently from 927514b to 8b67a13 Compare May 26, 2021 14:18

mkurc-ant force-pushed the testarch-writer branch from 8b67a13 to dbdba22 Compare May 27, 2021 17:21

mtdudek force-pushed the testarch-writer branch from a92388a to 399355e Compare June 9, 2021 08:54

mtdudek reviewed Jun 9, 2021

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mtdudek force-pushed the testarch-writer branch from e2b7d27 to 1e0feb6 Compare June 15, 2021 14:26

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mtdudek force-pushed the testarch-writer branch from 1e0feb6 to 556d43c Compare June 15, 2021 15:01

acomodi suggested changes Jun 15, 2021

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mtdudek force-pushed the testarch-writer branch 3 times, most recently from 1e2ad36 to 86fc80b Compare June 16, 2021 09:46

mkurc-ant changed the title ~~[WIP] Python code for generating and writing test architecture~~ Python code for generating and writing test architecture Jun 16, 2021

mkurc-ant marked this pull request as ready for review June 16, 2021 09:55

acomodi approved these changes Jun 16, 2021

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acomodi requested a review from gatecat June 16, 2021 12:09

acomodi mentioned this pull request Jun 16, 2021

Add support to emit VTR XML architecture file #101

Open

tmichalak mentioned this pull request Jun 17, 2021

device: add timing delay specification chipsalliance/fpga-interchange-schema#38

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gatecat reviewed Jun 18, 2021

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mkurc-ant and others added 13 commits June 21, 2021 13:30

Added a Makefile parameter for specifying concrete Python version

e964aee

Signed-off-by: Maciej Kurc <mkurc@antmicro.com> Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

WIP code for generating and writing test architecture

02e80a0

Signed-off-by: Maciej Kurc <mkurc@antmicro.com> Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

Add power site, as fabric need access to VCC and GND constants.

3d700c6

Add dummy tile on 0,0 location in generate_testarch as populate_chip needs this tile to be empty Add gen_device_config.yaml for testarch Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

Change IOPAD site to contain IO buffers

454850d

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

Change OPAD and IPAD to logic bel category

3caced3

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

Add CI testing for testarch

3b58a0c

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

Change VCC nad GND bels to logic type

c49705e

Fix primitives names to use global names Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

Add nextpnr_emit to testarch_device testing

fdc647b

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

Add constant wire sources to PWR tile

4fe81b8

Const wire now passes Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

Fix missing arguments in testarch_device.sh

ef4a627

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

Fix testarch_test.sh

f0334e0

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

Add license information to device_resource_builder and generate_testarch

85561b9

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

Auto formatting

218ee51

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

mtdudek force-pushed the testarch-writer branch from 86fc80b to 0d04bcb Compare June 21, 2021 11:30

Note possible future change to single pad for input and output

82352b5

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

mtdudek force-pushed the testarch-writer branch from 0d04bcb to 82352b5 Compare June 21, 2021 11:32

acomodi merged commit fade094 into chipsalliance:master Jun 23, 2021

acomodi deleted the testarch-writer branch June 23, 2021 16:12

acomodi restored the testarch-writer branch June 23, 2021 16:12

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Python code for generating and writing test architecture #85

Python code for generating and writing test architecture #85

mkurc-ant commented May 19, 2021

gatecat May 19, 2021

mkurc-ant May 20, 2021

mtdudek commented Jun 9, 2021

mtdudek Jun 9, 2021

gatecat Jun 9, 2021

mtdudek Jun 9, 2021 •

edited

gatecat Jun 9, 2021

mtdudek commented Jun 14, 2021 •

edited

gatecat Jun 15, 2021

acomodi left a comment

acomodi left a comment

gatecat Jun 18, 2021

gatecat Jun 18, 2021

gatecat Jun 18, 2021

acomodi Jun 21, 2021

acomodi commented Jun 21, 2021

Python code for generating and writing test architecture #85

Python code for generating and writing test architecture #85

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mkurc-ant commented May 19, 2021

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mtdudek commented Jun 14, 2021 • edited

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acomodi commented Jun 21, 2021

mtdudek Jun 9, 2021 •

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mtdudek commented Jun 14, 2021 •

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