Refactoring to make extension easier

chipsalliance · Jun 30, 2019 · 23ad2e9 · 23ad2e9
1 parent 06d321d
commit 23ad2e9
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Showing 2 changed files with 35 additions and 13 deletions.
diff --git a/run b/run
@@ -51,16 +51,20 @@ SIM_ONLY=0
 # Compile only
 CMP_ONLY=0
 
-# Run time options
-OPTS=""
+# Compile/run time options
+SIM_OPTS=""
+CMP_OPTS=""
 
 # Verbose logging, by default disable detail logging
 VERBOSE=0
 
 # Submit to LSF
-LSF_CMD="bsub"
+LSF_CMD="bsub -q eda_high"
 LSF=0
 
+# Testlist for regression
+TEST_LIST=testlist
+
 # Process command line options
 while [[ $# -gt 0 ]]
 do
@@ -82,8 +86,16 @@ case $key in
     SEED="$2"
     shift
     ;;
-    -opts)
-    OPTS="$2"
+    -sim_opts)
+    SIM_OPTS="$2"
+    shift
+    ;;
+    -cmp_opts)
+    CMP_OPTS="$2"
+    shift
+    ;;
+    -testlist)
+    TEST_LIST="$2"
     shift
     ;;
     -so)
@@ -123,7 +135,7 @@ if [[ "$SIMULATOR" == "vcs" ]]; then
                    -f ./files.f -full64 \
                    -l $OUT/compile.log  \
                    -Mdir=$OUT/vcs_simv.csrc \
-                   -o $OUT/vcs_simv"
+                   -o $OUT/vcs_simv ${CMP_OPTS}"
 
   SIM_CMD="$OUT/vcs_simv +UVM_TESTNAME="
 
@@ -135,7 +147,7 @@ elif [[ "$SIMULATOR" == "irun" ]]; then
                     -q -sv -uvm  \
                     -vlog_ext +.vh -I. \
                     -uvmhome CDNS-1.2 \
-                    -l ${OUT}/compile.log"
+                    -l ${OUT}/compile.log ${CMP_OPTS}"
 
   SIM_CMD="irun -R +UVM_TESTNAME="
 
@@ -172,10 +184,10 @@ fi
 
 # Run sim
 if [[ ${TEST} == "all" ]]; then
-  echo "Running regression with testlist:"
+  echo "Running regression with testlist: $TEST_LIST"
   LOG_LIST="${OUT}/sim_log.list"
   PROGRAM_CNT=0
-  cat testlist
+  cat "$TEST_LIST"
   rm -rf "$LOG_LIST"
   while read line; do
     if ! [[ $line =~ ^\/\/ ]]; then
@@ -187,7 +199,7 @@ if [[ ${TEST} == "all" ]]; then
         if [[ ${ITERATION} != "0" ]]; then
           echo "Running ${TEST} to generate ${ITERATION} tests"
           CMD="${SIM_CMD}${TEST} +asm_file_name=${OUT}/asm_tests/${TEST} \
-               +ntb_random_seed=${SEED} ${TEST_OPTS} ${OPTS} \
+               +ntb_random_seed=${SEED} ${TEST_OPTS} ${SIM_OPTS} \
                -l ${OUT}/sim_${TEST}.log +num_of_tests=${ITERATION}"
           ((PROGRAM_CNT+=$ITERATION))
           echo "${OUT}/sim_${TEST}.log" >> ${LOG_LIST}
@@ -199,7 +211,7 @@ if [[ ${TEST} == "all" ]]; then
         fi
       fi
     fi
-  done < testlist
+  done < $TEST_LIST
   # Wait util all tests are generated
   if [[ $LSF == 1 ]]; then
     TOTAL_CNT=`wc -l < ${LOG_LIST}`
@@ -227,7 +239,7 @@ else
   CMD="${SIM_CMD}${TEST} +asm_file_name=${OUT}/asm_tests/${TEST} \
                     +ntb_random_seed=${SEED} \
                     -l ${OUT}/sim_${TEST}.log \
-                    +num_of_tests=${NUM_TESTS} ${OPTS}"
+                    +num_of_tests=${NUM_TESTS} ${SIM_OPTS}"
   if [[ $VERBOSE == 1 ]]; then
     ${CMD}
   else

diff --git a/src/riscv_instr_pkg.sv b/src/riscv_instr_pkg.sv
@@ -22,6 +22,8 @@ package riscv_instr_pkg;
   `include "dv_defines.svh"
   `include "riscv_defines.svh"
 
+  `define include_file(f) `include "``f``"
+
   typedef enum bit [3:0] {
     BARE = 4'b0000,
     SV32 = 4'b0001,
@@ -613,7 +615,11 @@ package riscv_instr_pkg;
     STORE_AMO_PAGE_FAULT           = 4'hF
   } exception_cause_t;
 
-  `include "../setting/riscv_core_setting.sv"
+  `ifndef RISCV_CORE_SETTING
+    `define RISCV_CORE_SETTING ../setting/riscv_core_setting.sv
+  `endif
+
+  `include_file(`RISCV_CORE_SETTING)
 
   typedef bit [15:0] program_id_t;
 
@@ -754,4 +760,8 @@ package riscv_instr_pkg;
   `include "riscv_instr_sequence.sv"
   `include "riscv_asm_program_gen.sv"
 
+  `ifdef RISCV_DV_EXT_FILE_LIST
+    `include_file(`RISCV_DV_EXT_FILE_LIST)
+  `endif
+
 endpackage