Fix mstatus randomization issue (#168)

chipsalliance · Sep 18, 2019 · 80d4294 · 80d4294
1 parent 52d5ede
commit 80d4294
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Showing 4 changed files with 9 additions and 10 deletions.
diff --git a/src/riscv_asm_program_gen.sv b/src/riscv_asm_program_gen.sv
@@ -314,7 +314,7 @@ class riscv_asm_program_gen extends uvm_object;
   // Generate the user stack section
   virtual function void gen_stack_section();
     instr_stream.push_back(".pushsection .user_stack,\"aw\",@progbits;");
-    instr_stream.push_back($sformatf(".align %0d", $clog2(XLEN)));
+    instr_stream.push_back(".align 12");
     instr_stream.push_back("_user_stack_start:");
     instr_stream.push_back($sformatf(".rept %0d", cfg.stack_len - 1));
     instr_stream.push_back($sformatf(".%0dbyte 0x0", XLEN/8));
@@ -327,7 +327,7 @@ class riscv_asm_program_gen extends uvm_object;
   // The kernal stack is used to save user program context before executing exception handling
   virtual function void gen_kernel_stack_section();
     instr_stream.push_back(".pushsection .kernel_stack,\"aw\",@progbits;");
-    instr_stream.push_back($sformatf(".align %0d", $clog2(XLEN)));
+    instr_stream.push_back(".align 12");
     instr_stream.push_back("_kernel_stack_start:");
     instr_stream.push_back($sformatf(".rept %0d", cfg.kernel_stack_len - 1));
     instr_stream.push_back($sformatf(".%0dbyte 0x0", XLEN/8));

diff --git a/src/riscv_instr_gen_config.sv b/src/riscv_instr_gen_config.sv
@@ -49,9 +49,9 @@ class riscv_instr_gen_config extends uvm_object;
   // Priviledged mode after boot
   rand privileged_mode_t init_privileged_mode;
 
-  rand bit[XLEN-1:0] mstatus, mie,
-                     sstatus, sie,
-                     ustatus, uie;
+  rand bit[XLEN-1:0]     mstatus, mie,
+                         sstatus, sie,
+                         ustatus, uie;
 
   // Key fields in xSTATUS
   // Memory protection bits
@@ -286,7 +286,7 @@ class riscv_instr_gen_config extends uvm_object;
   // You can modify this constraint if your ISS support different set of delegations
   constraint delegation_c {
     foreach(m_mode_exception_delegation[i]) {
-      if(!support_supervisor_mode) {
+      if(!support_supervisor_mode || no_delegation) {
         m_mode_exception_delegation[i] == 0;
       }
       if(!(i inside {INSTRUCTION_ADDRESS_MISALIGNED, BREAKPOINT, ECALL_UMODE,
@@ -295,7 +295,7 @@ class riscv_instr_gen_config extends uvm_object;
       }
     }
     foreach(m_mode_interrupt_delegation[i]) {
-      if(!support_supervisor_mode) {
+      if(!support_supervisor_mode || no_delegation) {
         m_mode_interrupt_delegation[i] == 0;
       }
       if(!(i inside {S_SOFTWARE_INTR, S_TIMER_INTR, S_EXTERNAL_INTR})) {

diff --git a/src/riscv_privileged_common_seq.sv b/src/riscv_privileged_common_seq.sv
@@ -55,10 +55,8 @@ class riscv_privileged_common_seq extends uvm_sequence;
   virtual function void setup_mmode_reg(privileged_mode_t mode, ref riscv_privil_reg regs[$]);
     mstatus = riscv_privil_reg::type_id::create("mstatus");
     mstatus.init_reg(MSTATUS);
-    `uvm_info(`gfn, $sformatf("mstatus_val: 0x%0x", cfg.mstatus), UVM_LOW)
     mstatus.set_val({cfg.mstatus[XLEN-1:XLEN-21], cfg.mstatus_tvm, cfg.mstatus_mxr,
                      cfg.mstatus_sum, cfg.mstatus_mprv, cfg.mstatus[16:0]});
-    `DV_CHECK_RANDOMIZE_FATAL(mstatus, "cannot randomize mstatus");
     if(XLEN==64) begin
       mstatus.set_field("UXL", 2'b10);
       mstatus.set_field("SXL", 2'b10);
@@ -80,6 +78,7 @@ class riscv_privileged_common_seq extends uvm_sequence;
     mstatus.set_field("SIE",  cfg.enable_interrupt);
     mstatus.set_field("UPIE", cfg.enable_interrupt);
     mstatus.set_field("UIE", riscv_instr_pkg::support_umode_trap);
+    `uvm_info(`gfn, $sformatf("mstatus_val: 0x%0x", mstatus.get_val()), UVM_LOW)
     regs.push_back(mstatus);
     // Enable external and timer interrupt
     if (MIE inside {implemented_csr}) begin

diff --git a/test/riscv_instr_base_test.sv b/test/riscv_instr_base_test.sv
@@ -97,13 +97,13 @@ class riscv_instr_base_test extends uvm_test;
     for(int i = 0; i < cfg.num_of_tests; i++) begin
       string test_name;
       randomize_cfg();
+      cfg.build_instruction_template();
       asm_gen = riscv_asm_program_gen::type_id::create("asm_gen");
       get_directed_instr_stream_opts();
       asm_gen.cfg = cfg;
       test_name = $sformatf("%0s_%0d.S", asm_file_name, i);
       apply_directed_instr();
       `uvm_info(`gfn, "All directed instruction is applied", UVM_LOW)
-      cfg.build_instruction_template();
       asm_gen.gen_program();
       asm_gen.gen_test_file(test_name);
     end