Fix issue #4, change implementation to comply with old simulator

chipsalliance · Feb 16, 2019 · 97fd7ab · 97fd7ab
1 parent d18c2a7
commit 97fd7ab
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/src/riscv_instr_gen_config.sv b/src/riscv_instr_gen_config.sv
@@ -28,7 +28,7 @@ class riscv_instr_gen_config extends uvm_object;
   privileged_mode_t supported_privileged_mode[] = {USER_MODE, SUPERVISOR_MODE, MACHINE_MODE};
 
   // Unsupported instructions
-  riscv_instr_name_t unsupported_instr[] = {};
+  riscv_instr_name_t unsupported_instr[];
 
   // ISA supported by the processor
   riscv_instr_group_t supported_isa[] = {RV32I, RV32M, RV64I, RV64M, RV32C, RV64C};

diff --git a/src/riscv_loop_instr.sv b/src/riscv_loop_instr.sv
@@ -153,7 +153,7 @@ class riscv_loop_instr extends riscv_rand_instr_stream;
 
   // Build the whole loop structure from innermost loop to the outermost loop
   function void build_loop_instr_stream();
-    loop_instr = {};
+    loop_instr.delete;
     for(int i = 0; i < num_of_nested_loop; i++) begin
       loop_instr = {loop_init_instr[2*i],
                     loop_init_instr[2*i+1],