drop 'd' from TLBReq.dprv/dv also driven by instruction request

src/main/scala/rocket/DCache.scala

@@ -182,8 +182,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
     s0_tlb_req.vaddr := s0_req.addr
     s0_tlb_req.size := s0_req.size
     s0_tlb_req.cmd := s0_req.cmd
-    s0_tlb_req.dprv := s0_req.dprv
-    s0_tlb_req.dv := s0_req.dv
+    s0_tlb_req.prv := s0_req.dprv
+    s0_tlb_req.v := s0_req.dv
   }
   val s1_tlb_req = RegEnable(s0_tlb_req, s0_clk_en || tlb_port.req.valid)
 

src/main/scala/rocket/Frontend.scala

@@ -152,8 +152,8 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
   tlb.io.req.bits.vaddr := s1_pc
   tlb.io.req.bits.passthrough := Bool(false)
   tlb.io.req.bits.size := log2Ceil(coreInstBytes*fetchWidth)
-  tlb.io.req.bits.dprv := io.ptw.status.prv
-  tlb.io.req.bits.dv := io.ptw.status.v
+  tlb.io.req.bits.prv := io.ptw.status.prv
+  tlb.io.req.bits.v := io.ptw.status.v
   tlb.io.sfence := io.cpu.sfence
   tlb.io.kill := !s2_valid
 

src/main/scala/rocket/NBDcache.scala

@@ -726,8 +726,8 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
   dtlb.io.req.bits.vaddr := s1_req.addr
   dtlb.io.req.bits.size := s1_req.size
   dtlb.io.req.bits.cmd := s1_req.cmd
-  dtlb.io.req.bits.dprv := s1_req.dprv
-  dtlb.io.req.bits.dv := s1_req.dv
+  dtlb.io.req.bits.prv := s1_req.dprv
+  dtlb.io.req.bits.v := s1_req.dv
   when (!dtlb.io.req.ready && !io.cpu.req.bits.phys) { io.cpu.req.ready := Bool(false) }
 
   dtlb.io.sfence.valid := s1_valid && !io.cpu.s1_kill && s1_sfence

src/main/scala/rocket/TLB.scala

@@ -35,8 +35,8 @@ class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) {
   val passthrough = Bool()
   val size = UInt(width = log2Ceil(lgMaxSize + 1))
   val cmd  = Bits(width = M_SZ)
-  val dprv = UInt(PRV.SZ.W)
-  val dv = Bool()
+  val prv = UInt(PRV.SZ.W)
+  val v = Bool()
 
   override def cloneType = new TLBReq(lgMaxSize).asInstanceOf[this.type]
 }
@@ -201,8 +201,8 @@ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: T
   val r_vstage1_en = Reg(Bool())
   val r_stage2_en = Reg(Bool())
 
-  val priv = io.req.bits.dprv
-  val priv_v = usingHypervisor && io.req.bits.dv
+  val priv = io.req.bits.prv
+  val priv_v = usingHypervisor && io.req.bits.v
   val priv_s = priv(0)
   val priv_uses_vm = priv <= PRV.S
   val satp = Mux(priv_v, io.ptw.vsatp, io.ptw.ptbr)