Set TLRAM setName based on devName

chipsalliance · May 1, 2024 · 0b556a1 · 0b556a1
1 parent cc1395b
commit 0b556a1
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/tilelink/SRAM.scala b/src/main/scala/tilelink/SRAM.scala
@@ -50,7 +50,7 @@ class TLRAM(
       supportsPutFull    = TransferSizes(1, beatBytes),
       supportsArithmetic = if (atomics) TransferSizes(1, beatBytes) else TransferSizes.none,
       supportsLogical    = if (atomics) TransferSizes(1, beatBytes) else TransferSizes.none,
-      fifoId             = Some(0))), // requests are handled in order
+      fifoId             = Some(0)).v2copy(name=devName)), // requests are handled in order
     beatBytes  = beatBytes,
     minLatency = 1))) // no bypass needed for this device