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Merge remote-tracking branch 'origin/dev' into ifv
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jerryz123 committed Apr 19, 2024
2 parents b613fbe + 87b3a4d commit 3bd6174
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9 changes: 6 additions & 3 deletions src/main/scala/devices/debug/APB.scala
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@@ -1,10 +1,13 @@
// See LICENSE.SiFive for license details.

package freechips.rocketchip.devices.debug

import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.amba.apb.{APBRegisterNode}
import org.chipsalliance.diplomacy.lazymodule._

import freechips.rocketchip.amba.apb.APBRegisterNode
import freechips.rocketchip.diplomacy.AddressSet
import freechips.rocketchip.regmapper.RegField

case object APBDebugRegistersKey extends Field[Map[Int, Seq[RegField]]](Map())

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9 changes: 6 additions & 3 deletions src/main/scala/devices/debug/Custom.scala
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Expand Up @@ -3,10 +3,13 @@
package freechips.rocketchip.devices.debug

import chisel3._
import chisel3.experimental._
import chisel3.util._
import chisel3.experimental.SourceInfo
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.Parameters

import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._

case class DebugCustomParams(
addrs: List[Int],
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9 changes: 6 additions & 3 deletions src/main/scala/devices/debug/DMI.scala
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Expand Up @@ -4,10 +4,13 @@ package freechips.rocketchip.devices.debug

import chisel3._
import chisel3.util._

import org.chipsalliance.cde.config._
import freechips.rocketchip.util._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import org.chipsalliance.diplomacy.lazymodule._

import freechips.rocketchip.diplomacy.TransferSizes
import freechips.rocketchip.tilelink.{TLClientNode, TLMasterParameters, TLMasterPortParameters, TLMasterToSlaveTransferSizes}
import freechips.rocketchip.util.ParameterizedBundle

/** Constant values used by both Debug Bus Response & Request
*/
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26 changes: 15 additions & 11 deletions src/main/scala/devices/debug/Debug.scala
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Expand Up @@ -5,24 +5,28 @@ package freechips.rocketchip.devices.debug

import chisel3._
import chisel3.util._

import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import org.chipsalliance.diplomacy.lazymodule._

import freechips.rocketchip.amba.apb.{APBFanout, APBToTL}
import freechips.rocketchip.devices.debug.systembusaccess.{SBToTL, SystemBusAccessModule}
import freechips.rocketchip.devices.tilelink.{DevNullParams, TLBusBypass, TLError}
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice}
import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters, IntSyncCrossingSource, IntSyncIdentityNode}
import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn}
import freechips.rocketchip.rocket.{CSRs, Instructions}
import freechips.rocketchip.tile.MaxHartIdBits
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError}
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._
import freechips.rocketchip.devices.debug.systembusaccess._
import freechips.rocketchip.devices.tilelink.TLBusBypass
import freechips.rocketchip.amba.apb.{APBToTL, APBFanout}
import freechips.rocketchip.tilelink.{TLAsyncCrossingSink, TLAsyncCrossingSource, TLBuffer, TLRegisterNode, TLXbar}
import freechips.rocketchip.util.{Annotated, AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle}

import freechips.rocketchip.util.SeqBoolBitwiseOps
import freechips.rocketchip.util.SeqToAugmentedSeq
import freechips.rocketchip.util.BooleanToAugmentedBoolean

object DsbBusConsts {
def sbAddrWidth = 12
def sbIdWidth = 10

def sbIdWidth = 10
}

object DsbRegAddrs{
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25 changes: 14 additions & 11 deletions src/main/scala/devices/debug/Periphery.scala
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Expand Up @@ -3,18 +3,21 @@
package freechips.rocketchip.devices.debug

import chisel3._
import chisel3.experimental.{IntParam, noPrefix}
import chisel3.experimental.{noPrefix, IntParam}
import chisel3.util._
import chisel3.util.HasBlackBoxResource
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.amba.apb._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.jtag._
import freechips.rocketchip.util._
import freechips.rocketchip.prci.{ClockSinkParameters, ClockSinkNode}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts.{NullIntSyncSource, IntSyncXbar}

import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._

import freechips.rocketchip.amba.apb.{APBBundle, APBBundleParameters, APBMasterNode, APBMasterParameters, APBMasterPortParameters}
import freechips.rocketchip.interrupts.{IntSyncXbar, NullIntSyncSource}
import freechips.rocketchip.jtag.JTAGIO
import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters}
import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, FBUS, ResetSynchronous, SubsystemResetSchemeKey, TLBusWrapperLocation}
import freechips.rocketchip.tilelink.{TLFragmenter, TLWidthWidget}
import freechips.rocketchip.util.{AsyncResetSynchronizerShiftReg, CanHavePSDTestModeIO, ClockGate, PSDTestMode, PlusArg, ResetSynchronizerShiftReg}

import freechips.rocketchip.util.BooleanToAugmentedBoolean

/** Protocols used for communicating with external debugging tools */
sealed trait DebugExportProtocol
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13 changes: 8 additions & 5 deletions src/main/scala/devices/debug/SBA.scala
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Expand Up @@ -4,13 +4,16 @@ package freechips.rocketchip.devices.debug.systembusaccess

import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._

import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import org.chipsalliance.diplomacy.lazymodule._

import freechips.rocketchip.amba.{AMBAProt, AMBAProtField}
import freechips.rocketchip.devices.debug.{DebugModuleKey, RWNotify, SBCSFields, WNotifyVal}
import freechips.rocketchip.diplomacy.TransferSizes
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup, RegFieldWrType}
import freechips.rocketchip.tilelink.{TLClientNode, TLMasterParameters, TLMasterPortParameters}
import freechips.rocketchip.util.property
import freechips.rocketchip.devices.debug._

object SystemBusAccessState extends scala.Enumeration {
type SystemBusAccessState = Value
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12 changes: 8 additions & 4 deletions src/main/scala/devices/tilelink/BootROM.scala
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Expand Up @@ -3,11 +3,15 @@
package freechips.rocketchip.devices.tilelink

import chisel3._
import chisel3.util.log2Ceil
import org.chipsalliance.cde.config.{Field, Parameters}
import chisel3.util._

import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._

import freechips.rocketchip.diplomacy.{AddressSet, RegionType, Resource, SimpleDevice, TransferSizes}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.tilelink.{TLFragmenter, TLManagerNode, TLSlaveParameters, TLSlavePortParameters}

import java.nio.ByteBuffer
import java.nio.file.{Files, Paths}
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9 changes: 6 additions & 3 deletions src/main/scala/devices/tilelink/BusBlocker.scala
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Expand Up @@ -3,10 +3,13 @@
package freechips.rocketchip.devices.tilelink

import chisel3._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp, SimpleDevice}

import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._

import freechips.rocketchip.diplomacy.{AddressSet, SimpleDevice}
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc}
import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode, TLBusWrapper, TLNameNode, TLNode}
import freechips.rocketchip.tilelink.{TLBusWrapper, TLFragmenter, TLNameNode, TLNode, TLRegisterNode}

/** Parameterize a BasicBusBlocker.
*
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19 changes: 11 additions & 8 deletions src/main/scala/devices/tilelink/CLINT.scala
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Expand Up @@ -3,14 +3,17 @@
package freechips.rocketchip.devices.tilelink

import chisel3._
import chisel3.util.ShiftRegister
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import chisel3.util._

import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._

import freechips.rocketchip.diplomacy.{AddressSet, Resource, SimpleDevice}
import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters}
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}
import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode}
import freechips.rocketchip.util.Annotated

object CLINTConsts
{
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9 changes: 5 additions & 4 deletions src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala
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Expand Up @@ -2,9 +2,11 @@

package freechips.rocketchip.devices.tilelink

import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._

import freechips.rocketchip.diplomacy.{AddressSet, BufferParams}
import freechips.rocketchip.tilelink.{HasTLBusParams, TLBuffer, TLCacheCork, TLCacheCorkParams, TLFragmenter, TLOutwardNode, TLTempNode}

case class BuiltInZeroDeviceParams(
addr: AddressSet,
Expand Down Expand Up @@ -63,4 +65,3 @@ object BuiltInDevices {
trait CanHaveBuiltInDevices {
def builtInDevices: BuiltInDevices
}

14 changes: 8 additions & 6 deletions src/main/scala/devices/tilelink/ClockBlocker.scala
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Expand Up @@ -3,12 +3,14 @@
package freechips.rocketchip.devices.tilelink

import chisel3._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._

import freechips.rocketchip.diplomacy.{AddressSet, SimpleDevice}
import freechips.rocketchip.prci.ClockAdapterNode
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc}
import freechips.rocketchip.tilelink.TLRegisterNode
import freechips.rocketchip.util.ClockGate

/** This device extends a basic bus blocker by allowing it to gate the clocks of the device
* whose tilelink port is being blocked. For now it is only possible to block
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10 changes: 7 additions & 3 deletions src/main/scala/devices/tilelink/DevNull.scala
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Expand Up @@ -2,9 +2,13 @@

package freechips.rocketchip.devices.tilelink

import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._

import freechips.rocketchip.diplomacy.{AddressSet, HasClockDomainCrossing, RegionType, SimpleDevice, TransferSizes}
import freechips.rocketchip.tilelink.{TLManagerNode, TLSlaveParameters, TLSlavePortParameters}

import freechips.rocketchip.tilelink.TLClockDomainCrossing

case class DevNullParams(
address: Seq[AddressSet],
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9 changes: 6 additions & 3 deletions src/main/scala/devices/tilelink/Error.scala
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Expand Up @@ -4,9 +4,12 @@ package freechips.rocketchip.devices.tilelink

import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._

import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._

import freechips.rocketchip.diplomacy.SimpleDevice
import freechips.rocketchip.tilelink.{TLArbiter, TLMessages, TLPermissions}

/** Adds a /dev/null slave that generates TL error response messages */
class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters)
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13 changes: 9 additions & 4 deletions src/main/scala/devices/tilelink/MaskROM.scala
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Expand Up @@ -4,11 +4,16 @@ package freechips.rocketchip.devices.tilelink

import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._

import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._

import freechips.rocketchip.diplomacy.{AddressSet, RegionType, SimpleDevice, TransferSizes}
import freechips.rocketchip.subsystem.{Attachable, HierarchicalLocation, TLBusWrapperLocation}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink.{TLFragmenter, TLManagerNode, TLSlaveParameters, TLSlavePortParameters, TLWidthWidget}
import freechips.rocketchip.util.{ROMConfig, ROMGenerator}

import freechips.rocketchip.util.DataToAugmentedData

case class MaskROMParams(address: BigInt, name: String, depth: Int = 2048, width: Int = 32)

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14 changes: 11 additions & 3 deletions src/main/scala/devices/tilelink/MasterMux.scala
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Expand Up @@ -3,9 +3,17 @@
package freechips.rocketchip.devices.tilelink

import chisel3._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._

import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._

import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rocketchip.tilelink.{
LFSR64, TLBundleA, TLBundleC, TLBundleE, TLClientNode, TLCustomNode, TLFilter, TLFragmenter,
TLFuzzer, TLMasterParameters, TLMasterPortParameters, TLPermissions, TLRAM, TLRAMModel,
TLSlaveParameters, TLSlavePortParameters
}

class MasterMuxNode(uFn: Seq[TLMasterPortParameters] => TLMasterPortParameters)(implicit valName: ValName) extends TLCustomNode
{
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14 changes: 9 additions & 5 deletions src/main/scala/devices/tilelink/PhysicalFilter.scala
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Expand Up @@ -4,11 +4,15 @@ package freechips.rocketchip.devices.tilelink

import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._

import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._

import freechips.rocketchip.diplomacy.{AddressSet, SimpleDevice}
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn}
import freechips.rocketchip.tilelink.{TLAdapterNode, TLMessages, TLPermissions, TLRegisterNode}

import freechips.rocketchip.util.DataToAugmentedData

case class DevicePMPParams(addressBits: Int, pageBits: Int)

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23 changes: 14 additions & 9 deletions src/main/scala/devices/tilelink/Plic.scala
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Expand Up @@ -3,19 +3,24 @@
package freechips.rocketchip.devices.tilelink

import chisel3._
import chisel3.experimental._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
import chisel3.experimental.SourceInfo

import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._

import freechips.rocketchip.diplomacy.{AddressSet, Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice}
import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters}
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn}
import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}
import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode}
import freechips.rocketchip.util.{Annotated, MuxT, property}

import scala.math.min

import freechips.rocketchip.util.UIntToAugmentedUInt
import freechips.rocketchip.util.SeqToAugmentedSeq

class GatewayPLICIO extends Bundle {
val valid = Output(Bool())
val ready = Input(Bool())
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9 changes: 6 additions & 3 deletions src/main/scala/devices/tilelink/TestRAM.scala
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Expand Up @@ -4,9 +4,12 @@ package freechips.rocketchip.devices.tilelink

import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._

import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._

import freechips.rocketchip.diplomacy.{AddressSet, MemoryDevice, RegionType, TransferSizes}
import freechips.rocketchip.tilelink.{TLDelayer, TLFuzzer, TLManagerNode, TLMessages, TLRAMModel, TLSlaveParameters, TLSlavePortParameters}

// Do not use this for synthesis! Only for simulation.
class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, trackCorruption: Boolean = true)(implicit p: Parameters) extends LazyModule
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