fix: S-interpolator for assert, assume and printf

src/main/scala/amba/axi4/Deinterleaver.scala

@@ -72,7 +72,7 @@ class AXI4Deinterleaver(maxReadBytes: Int, buffer: BufferParams = BufferParams.d
             // correct type.
             val q = Wire(new QueueIO(out.r.bits.cloneType, beats))
             q.suggestName(s"queue_wire_${i}")
-            assert(!q.enq.valid, s"ID ${i} should not be used")
+            chisel3.assert(!q.enq.valid, "ID ${i} should not be used")
             q := DontCare
             q
           }

src/main/scala/devices/debug/Debug.scala

@@ -1502,8 +1502,8 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
     }
 
     val flags = WireInit(VecInit(Seq.fill(1 << selectedHartReg.getWidth) {0.U.asTypeOf(new flagBundle())} ))
-    assert ((hartSelFuncs.hartSelToHartId(selectedHartReg) < flags.size.U),
-      s"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < ${flags.size} for it to work.")
+    chisel3.assert ((hartSelFuncs.hartSelToHartId(selectedHartReg) < flags.size.U),
+      "HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < ${flags.size} for it to work.")
     flags(hartSelFuncs.hartSelToHartId(selectedHartReg)).go := goReg
 
     for (component <- 0 until nComponents) {

src/main/scala/formal/FormalUtils.scala

@@ -68,24 +68,24 @@ object Property {
     val src_wrap = s"@[${proposed_src}]"
     if (dir==MonitorDirection.Monitor) {
       when(!cond) {
-        printf(s"assert:${proposed_src}:${prop_type.toString} ${message + "_" + line_info}")
+        printf(cf"assert:${proposed_src}:${prop_type.toString} ${message + "_" + line_info}")
       }
     } else if (dir==MonitorDirection.Receiver) {
       when(!cond) {
-        printf(s"assert:${proposed_src}:${prop_type.toString} ${message + "_" + line_info}")
+        printf(cf"assert:${proposed_src}:${prop_type.toString} ${message + "_" + line_info}")
       }
     } else if (dir==MonitorDirection.Driver) {
       when(!cond) {
-        printf(s"assume:${proposed_src}:${prop_type.toString} ${message + "_" + line_info}")
+        printf(cf"assume:${proposed_src}:${prop_type.toString} ${message + "_" + line_info}")
       }
     } else if (dir==MonitorDirection.Cover) {
         if (prop_type==PropertyClass.CoverDisableMonitor) {
           when(cond) { //We want to assert that the condition is never true, which is opposite of a normal assertion
-            printf(s"assert:${proposed_src}:${prop_type.toString} ${message + "_" + line_info}")
+            printf(cf"assert:${proposed_src}:${prop_type.toString} ${message + "_" + line_info}")
           }
         } else {
             when(cond) {
-              printf(s"cover:${proposed_src}:${prop_type.toString} ${message + "_" + line_info}")
+              printf(cf"cover:${proposed_src}:${prop_type.toString} ${message + "_" + line_info}")
             }
         }
     }

src/main/scala/groundtest/TraceGen.scala

@@ -585,7 +585,7 @@ class TraceGenerator(val params: TraceGenParams)(implicit val p: Parameters) ext
 
   // Emit that this thread has completed
   when (donePulse) {
-    printf(s"FINISHED ${numGens}\n")
+    printf(cf"FINISHED ${numGens}\n")
   }
 
   io.finished := done
@@ -631,5 +631,5 @@ class TraceGenTileModuleImp(outer: TraceGenTile) extends GroundTestTileModuleImp
   status.timeout.bits := 0.U
   status.error.valid := false.B
 
-  assert(!tracegen.io.timeout, s"TraceGen tile ${outer.tileParams.hartId}: request timed out")
+  assert(!tracegen.io.timeout, cf"TraceGen tile ${outer.tileParams.hartId}: request timed out")
 }

src/main/scala/rocket/Events.scala

@@ -17,7 +17,7 @@ class EventSet(val gate: (UInt, UInt) => Bool, val events: Seq[(String, () => Bo
   }
   def dump(): Unit = {
     for (((name, _), i) <- events.zipWithIndex)
-      when (check(1.U << i)) { printf(s"Event $name\n") }
+      when (check(1.U << i)) { printf(cf"Event $name\n") }
   }
   def withCovers: Unit = {
     events.zipWithIndex.foreach {

src/main/scala/tilelink/Arbiter.scala

@@ -197,7 +197,7 @@ class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(impli
 {
   def assertLowest(id: Int): Unit = {
     when (sources(id).valid) {
-      assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.")
+      chisel3.assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), "$id was valid but a higher valid source was granted ready.")
     }
   }
 
@@ -212,7 +212,7 @@ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(impl
 {
   def assertHighest(id: Int): Unit = {
     when (sources(id).valid) {
-      assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.")
+      chisel3.assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), "$id was valid but a lower valid source was granted ready.")
     }
   }
 

src/main/scala/tilelink/PatternPusher.scala

@@ -71,7 +71,7 @@ class TLPatternPusher(name: String, pattern: Seq[Pattern])(implicit p: Parameter
     }
 
     val (plegal, pbits) = pattern.map(_.bits(edgeOut)).unzip
-    assert (end || Vec(plegal)(step), s"Pattern pusher ${name} tried to push an illegal request")
+    chisel3.assert (end || Vec(plegal)(step), "Pattern pusher ${name} tried to push an illegal request")
 
     a.valid := io.run && ready && !end && !flight
     a.bits  := Vec(pbits)(step)

src/main/scala/unittest/UnitTest.scala

@@ -28,10 +28,10 @@ trait UnitTestModule extends MultiIOModule with HasUnitTestIO {
 abstract class UnitTest(val timeout: Int = 4096) extends Module with UnitTestLegacyModule {
   val testName = this.getClass.getSimpleName
 
-  when (io.start) { printf(s"Started UnitTest $testName\n") }
+  when (io.start) { printf(cf"Started UnitTest $testName\n") }
 
   val timed_out = SimpleTimer(timeout, io.start, io.finished)
-  assert(!timed_out, s"UnitTest $testName timed out")
+  chisel3.assert(!timed_out, "UnitTest $testName timed out")
 }
 
 case object UnitTests extends Field[Parameters => Seq[UnitTest]]

src/main/scala/util/PlusArg.scala

@@ -61,7 +61,7 @@ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: Str
   })
   val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
   when (max > 0.U) {
-    assert (io.count < max, s"Timeout exceeded: $docstring")
+    chisel3.assert (io.count < max, "Timeout exceeded: $docstring")
   }
 }