subsystem: add some inter-wrapper buffer params

chipsalliance · Feb 23, 2018 · 820f759 · 820f759
1 parent ad823ef
commit 820f759
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Showing 2 changed files with 9 additions and 6 deletions.
diff --git a/src/main/scala/subsystem/PeripheryBus.scala b/src/main/scala/subsystem/PeripheryBus.scala
@@ -12,6 +12,7 @@ case class PeripheryBusParams(
   beatBytes: Int,
   blockBytes: Int,
   arithmeticAtomics: Boolean = true,
+  bufferAtomics: BufferParams = BufferParams.default,
   sbusCrossingType: SubsystemClockCrossing = SynchronousCrossing(), // relative to sbus
   frequency: BigInt = BigInt(100000000) // 100 MHz as default bus frequency
 ) extends HasTLBusParams
@@ -92,7 +93,7 @@ class PeripheryBus(params: PeripheryBusParams)
   def fromSystemBus(gen: => TLOutwardNode) {
     from("sbus") {
       (inwardNode
-        :*= TLBuffer(BufferParams.default)
+        :*= TLBuffer(params.bufferAtomics)
         :*= TLAtomicAutomata(arithmetic = params.arithmeticAtomics)
         :*= gen)
     }

diff --git a/src/main/scala/subsystem/SystemBus.scala b/src/main/scala/subsystem/SystemBus.scala
@@ -8,7 +8,10 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
 
-case class SystemBusParams(beatBytes: Int, blockBytes: Int) extends HasTLBusParams
+case class SystemBusParams(
+  beatBytes: Int,
+  blockBytes: Int,
+  pbusBuffer: BufferParams = BufferParams.none) extends HasTLBusParams
 
 case object SystemBusKey extends Field[SystemBusParams]
 
@@ -23,13 +26,12 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
 
   def busView = master_splitter.node.edges.in.head
 
-  def toPeripheryBus(buffer: BufferParams = BufferParams.none)
-                    (gen: => TLNode): TLOutwardNode = {
+  def toPeripheryBus(gen: => TLNode): TLOutwardNode = {
     to("pbus") {
       (gen
         := TLFIFOFixer(TLFIFOFixer.all)
         := TLWidthWidget(params.beatBytes)
-        := bufferTo(buffer))
+        := bufferTo(params.pbusBuffer))
     }
   }
 
@@ -52,7 +54,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
   }
 
   def toFixedWidthSlave[D,U,E,B <: Data]
-      (name: Option[String] = None, buffer: BufferParams = BufferParams.none)
+      (name: Option[String] = None, buffer: BufferParams = BufferParams.default)
       (gen: =>  NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
         TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
     to("slave" named name) { gen :*= fixedWidthTo(buffer) }