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fix: empty argument list (#3262)
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+ add `()` to those empty argument list function call;
Auto-application to `()` is deprecated. Supply the empty argument list `()` explicitly to invoke method
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SingularityKChen committed Jun 15, 2023
1 parent 9a1dc2d commit 9b383c5
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Showing 10 changed files with 10 additions and 10 deletions.
2 changes: 1 addition & 1 deletion src/main/scala/interrupts/Nodes.scala
Expand Up @@ -21,7 +21,7 @@ object IntImp extends SimpleNodeImp[IntSourcePortParameters, IntSinkPortParamete

trait IntFormatNode extends BaseNode
{
override def formatNode() = "Interrupt Node\n"
override def formatNode = "Interrupt Node\n"
}

case class IntSourceNode(portParams: Seq[IntSourcePortParameters])(implicit valName: ValName) extends SourceNode(IntImp)(portParams) with IntFormatNode
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2 changes: 1 addition & 1 deletion src/main/scala/jtag/JtagStateMachine.scala
Expand Up @@ -70,7 +70,7 @@ object JtagState {
class JtagStateMachine(implicit val p: Parameters) extends Module() {
class StateMachineIO extends Bundle {
val tms = Input(Bool())
val currState = Output(JtagState.State.chiselType)
val currState = Output(JtagState.State.chiselType())
}
val io = IO(new StateMachineIO)

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2 changes: 1 addition & 1 deletion src/main/scala/jtag/JtagTap.scala
Expand Up @@ -72,7 +72,7 @@ class JtagTapController(irLength: Int, initialInstruction: BigInt)(implicit val
// JTAG state machine
//

val currState = Wire(JtagState.State.chiselType)
val currState = Wire(JtagState.State.chiselType())

// At this point, the TRSTn should already have been
// combined with any POR, and it should also be
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2 changes: 1 addition & 1 deletion src/main/scala/subsystem/BaseSubsystem.scala
Expand Up @@ -31,7 +31,7 @@ abstract class BareSubsystemModuleImp[+L <: BareSubsystem](_outer: L) extends La
ElaborationArtefacts.add("graphml", outer.graphML)
ElaborationArtefacts.add("dts", outer.dts)
ElaborationArtefacts.add("json", outer.json)
ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader)
ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader())
println(outer.dts)
}

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2 changes: 1 addition & 1 deletion src/main/scala/tilelink/Arbiter.scala
Expand Up @@ -91,7 +91,7 @@ object TLArbiter

// Who wants access to the sink?
val earlyValids = sourcesIn.map(_.earlyValid)
val validQuals = sourcesIn.map(_.validQual)
val validQuals = sourcesIn.map(_.validQual())
// Arbitrate amongst the requests
val readys = VecInit(policy(earlyValids.size, Cat(earlyValids.reverse), latch).asBools)
// Which request wins arbitration?
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2 changes: 1 addition & 1 deletion src/main/scala/tilelink/AtomicAutomata.scala
Expand Up @@ -46,7 +46,7 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc

// Managers that need help with atomics must necessarily have this node as the root of a tree in the node graph.
// (But they must also ensure no sideband operations can get between the read and write.)
val violations = managersNeedingHelp.flatMap(_.findTreeViolation).map { node => (node.name, node.inputs.map(_._1.name)) }
val violations = managersNeedingHelp.flatMap(_.findTreeViolation()).map { node => (node.name, node.inputs.map(_._1.name)) }
require(violations.isEmpty,
s"AtomicAutomata can only help nodes for which it is at the root of a diplomatic node tree," +
"but the following violations were found:\n" +
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2 changes: 1 addition & 1 deletion src/main/scala/tilelink/Buffer.scala
Expand Up @@ -112,7 +112,7 @@ class TLBufferAndNotCancel(
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in.a.asDecoupled)
out.a <> a(in.a.asDecoupled())
in .d <> d(out.d)

if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
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2 changes: 1 addition & 1 deletion src/main/scala/unittest/UnitTest.scala
Expand Up @@ -22,7 +22,7 @@ trait UnitTestLegacyModule extends HasUnitTestIO {

trait UnitTestModule extends Module with HasUnitTestIO {
val io = IO(new Bundle with UnitTestIO)
ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader)
ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader())
}

abstract class UnitTest(val timeout: Int = 4096) extends Module with UnitTestLegacyModule {
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2 changes: 1 addition & 1 deletion src/main/scala/util/ReadyValidCancel.scala
Expand Up @@ -157,7 +157,7 @@ class ReadyValidCancelRRArbiter[T <: Data](gen: T, n: Int, rr: Boolean) extends
when (io.out.earlyValid) {
assert(selectEnc_q < n.U, "arbiter round-robin select out of range")
}
when (io.in(selectEnc_q).mightFire && io.in.map(i => i.earlyValid && !i.ready).orR) {
when (io.in(selectEnc_q).mightFire() && io.in.map(i => i.earlyValid && !i.ready).orR) {
assert(selectEnc_in =/= selectEnc_q, "arbiter round-robin select did not advance")
}
}
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2 changes: 1 addition & 1 deletion src/main/scala/util/package.scala
Expand Up @@ -68,7 +68,7 @@ package object util {
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~(): Seq[Bool] = x.map(!_)
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
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