Merge remote-tracking branch 'origin/boom-devel' into boom

src/main/scala/rocket/CSR.scala

@@ -153,7 +153,7 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle
   val interrupt = Bool(OUTPUT)
   val interrupt_cause = UInt(OUTPUT, xLen)
   val bp = Vec(nBreakpoints, new BP).asOutput
-  val events = Vec(nPerfEvents, UInt(log2Up(1+retireWidth))).asInput
+  val events = Vec(nPerfEvents, UInt(log2Up(1+perfIncWidth))).asInput
 }
 
 class CSRFile(implicit p: Parameters) extends CoreModule()(p)

src/main/scala/rocket/Frontend.scala

@@ -26,6 +26,12 @@ class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) {
   val replay = Bool()
 }
 
+class ExtBTBIO(implicit p: Parameters) extends CoreBundle()(p) {
+  val req = Valid(new BTBReq).flip
+  val resp = Valid(new BTBResp)
+  val icmiss = Bool(INPUT)
+}
+
 class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
   val req = Valid(new FrontendReq)
   val resp = Decoupled(new FrontendResp).flip
@@ -35,6 +41,8 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
   val flush_icache = Bool(OUTPUT)
   val flush_tlb = Bool(OUTPUT)
   val npc = UInt(INPUT, width = vaddrBitsExtended)
+
+  val ext_btb = new ExtBTBIO()
 }
 
 class Frontend(implicit p: Parameters) extends LazyModule {
@@ -106,7 +114,24 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
     s2_valid := Bool(false)
   }
 
-  if (usingBTB) {
+   // hack: boom will bring in its own BTB
+  if (usingExternalBTB) {
+    println("Frontend: using external BTB")
+    io.cpu.ext_btb.req.valid := false
+    io.cpu.ext_btb.req.bits.addr := io.cpu.npc
+    // need to know miss signal for when frontend replays requests or continues with requests despite stalling.
+    io.cpu.ext_btb.icmiss := icmiss
+    when (!stall && !icmiss) {
+      io.cpu.ext_btb.req.valid := true
+    }
+    when (io.cpu.ext_btb.resp.valid && io.cpu.ext_btb.resp.bits.taken) {
+      predicted_npc := io.cpu.ext_btb.resp.bits.target.sextTo(vaddrBitsExtended)
+      predicted_taken := Bool(true)
+    }
+  } else if (usingBTB) {
+    val btbParams = tileParams.btb.getOrElse(BTBParams(nEntries = 0))
+//    require (!tileParams.btb.get.updatesOutofOrder)
+    require (!btbParams.updatesOutOfOrder)
     val btb = Module(new BTB)
     btb.io.req.valid := false
     btb.io.req.bits.addr := s1_pc_

src/main/scala/rocket/Rocket.scala

@@ -20,6 +20,7 @@ case class RocketCoreParams(
   nBreakpoints: Int = 1,
   nPerfCounters: Int = 0,
   nPerfEvents: Int = 0,
+  perfIncWidth: Int = 1,
   nCustomMRWCSRs: Int = 0,
   mtvecInit: Option[BigInt] = Some(BigInt(0)),
   mtvecWritable: Boolean = true,
@@ -45,6 +46,7 @@ trait HasRocketCoreParameters extends HasCoreParameters {
   val nBreakpoints = rocketParams.nBreakpoints
   val nPerfCounters = rocketParams.nPerfCounters
   val nPerfEvents = rocketParams.nPerfEvents
+  val perfIncWidth = rocketParams.perfIncWidth
   val nCustomMrwCsrs = rocketParams.nCustomMRWCSRs
   val mtvecInit = rocketParams.mtvecInit
   val mtvecWritable = rocketParams.mtvecWritable

src/main/scala/tile/BaseTile.scala

@@ -30,6 +30,7 @@ trait HasTileParameters {
   val usingDebug = tileParams.core.useDebug
   val usingRoCC = !tileParams.rocc.isEmpty
   val usingBTB = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0
+  val usingExternalBTB = tileParams.btb.isDefined && tileParams.btb.get.nEntries == 0 && tileParams.btb.get.updatesOutOfOrder
   val usingPTW = usingVM
   val usingDataScratchpad = tileParams.dcache.isDefined && tileParams.dataScratchpadBytes > 0