TLClient/ManagerParameters -> TLMaster/SlaveParameters.v1

src/main/scala/amba/apb/ToTL.scala

@@ -11,9 +11,9 @@ import freechips.rocketchip.util._
 
 case class APBToTLNode()(implicit valName: ValName) extends MixedAdapterNode(APBImp, TLImp)(
   dFn = { mp =>
-    TLClientPortParameters(
+    TLMasterPortParameters.v1(
       clients = mp.masters.map { m =>
-        TLClientParameters(name = m.name, nodePath = m.nodePath)
+        TLMasterParameters.v1(name = m.name, nodePath = m.nodePath)
       },
       requestFields = AMBAProtField() +: mp.requestFields,
       responseKeys  = mp.responseKeys)

src/main/scala/amba/axi4/ToTL.scala

@@ -13,10 +13,10 @@ case class AXI4ToTLNode(wcorrupt: Boolean)(implicit valName: ValName) extends Mi
   dFn = { case mp =>
     mp.masters.foreach { m => require (m.maxFlight.isDefined, "AXI4 must include a transaction maximum per ID to convert to TL") }
     val maxFlight = mp.masters.map(_.maxFlight.get).max
-    TLClientPortParameters(
+    TLMasterPortParameters.v1(
       clients = mp.masters.filter(_.maxFlight != Some(0)).flatMap { m =>
         for (id <- m.id.start until m.id.end)
-          yield TLClientParameters(
+          yield TLMasterParameters.v1(
             name        = s"${m.name} ID#${id}",
             sourceId    = IdRange(id * maxFlight*2, (id+1) * maxFlight*2), // R+W ids are distinct
             nodePath    = m.nodePath,

src/main/scala/devices/debug/DMI.scala

@@ -84,7 +84,7 @@ class DMIToTL(implicit p: Parameters) extends LazyModule {
   // emitsGet = TransferSizes(4, 4),
   // emitsPutFull = TransferSizes(4, 4),
   // emitsPutPartial = TransferSizes(4, 4)
-  val node = TLClientNode(Seq(TLClientPortParameters(Seq(TLClientParameters("debug")))))
+  val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1("debug")))))
 
   lazy val module = new LazyModuleImp(this) {
     val io = IO(new Bundle {

src/main/scala/devices/debug/SBA.scala

@@ -265,7 +265,7 @@ class SBToTL(implicit p: Parameters) extends LazyModule {
 
   val cfg = p(DebugModuleKey).get
 
-  val node = TLClientNode(Seq(TLClientPortParameters(Seq(TLClientParameters("debug")))))
+  val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1("debug")))))
 
   lazy val module = new LazyModuleImp(this) {
     val io = IO(new Bundle {

src/main/scala/devices/tilelink/BootROM.scala

@@ -23,8 +23,8 @@ case object BootROMParams extends Field[BootROMParams]
 class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4,
   resources: Seq[Resource] = new SimpleDevice("rom", Seq("sifive,rom0")).reg("mem"))(implicit p: Parameters) extends LazyModule
 {
-  val node = TLManagerNode(Seq(TLManagerPortParameters(
-    Seq(TLManagerParameters(
+  val node = TLManagerNode(Seq(TLSlavePortParameters.v1(
+    Seq(TLSlaveParameters.v1(
       address     = List(AddressSet(base, size-1)),
       resources   = resources,
       regionType  = RegionType.UNCACHED,

src/main/scala/devices/tilelink/BusBypass.scala

@@ -16,8 +16,8 @@ abstract class TLBusBypassBase(beatBytes: Int, deadlock: Boolean = false)(implic
   val node = NodeHandle(nodeIn, nodeOut)
 
   protected val bar = LazyModule(new TLBusBypassBar(dFn = { mp =>
-    mp.copy(managers = mp.managers.map { m =>
-      m.copy(
+    mp.v1copy(managers = mp.managers.map { m =>
+      m.v1copy(
         mayDenyPut = m.mayDenyPut || !deadlock,
         mayDenyGet = m.mayDenyGet || !deadlock)
     })
@@ -43,19 +43,19 @@ class TLBusBypass(beatBytes: Int)(implicit p: Parameters) extends TLBusBypassBas
   }
 }
 
-class TLBypassNode(dFn: TLManagerPortParameters => TLManagerPortParameters)(implicit valName: ValName) extends TLCustomNode
+class TLBypassNode(dFn: TLSlavePortParameters => TLSlavePortParameters)(implicit valName: ValName) extends TLCustomNode
 {
   def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = {
     require (iStars == 0 && oStars == 0, "TLBypass node does not support :=* or :*=")
     require (iKnown == 1, "TLBypass node expects exactly one input")
     require (oKnown == 2, "TLBypass node expects exactly two outputs")
     (0, 0)
   }
-  def mapParamsD(n: Int, p: Seq[TLClientPortParameters]): Seq[TLClientPortParameters] = { p ++ p }
-  def mapParamsU(n: Int, p: Seq[TLManagerPortParameters]): Seq[TLManagerPortParameters] = { Seq(dFn(p.last)) }
+  def mapParamsD(n: Int, p: Seq[TLMasterPortParameters]): Seq[TLMasterPortParameters] = { p ++ p }
+  def mapParamsU(n: Int, p: Seq[TLSlavePortParameters]): Seq[TLSlavePortParameters] = { Seq(dFn(p.last)) }
 }
 
-class TLBusBypassBar(dFn: TLManagerPortParameters => TLManagerPortParameters)(implicit p: Parameters) extends LazyModule
+class TLBusBypassBar(dFn: TLSlavePortParameters => TLSlavePortParameters)(implicit p: Parameters) extends LazyModule
 {
   val node = new TLBypassNode(dFn)
 

src/main/scala/devices/tilelink/DevNull.scala

@@ -32,8 +32,8 @@ abstract class DevNullDevice(params: DevNullParams, beatBytes: Int, device: Simp
   val atom = if (params.maxAtomic > 0) TransferSizes(1, params.maxAtomic) else TransferSizes.none
   val acq  = if (params.acquire) xfer else TransferSizes.none
   val hint = if (params.hint) xfer else TransferSizes.none
-  val node = TLManagerNode(Seq(TLManagerPortParameters(
-    Seq(TLManagerParameters(
+  val node = TLManagerNode(Seq(TLSlavePortParameters.v1(
+    Seq(TLSlaveParameters.v1(
       address            = params.address,
       resources          = device.reg,
       regionType         = params.region,

src/main/scala/devices/tilelink/MaskROM.scala

@@ -12,8 +12,8 @@ case class MaskROMParams(address: BigInt, name: String, depth: Int = 2048, width
 
 class TLMaskROM(c: MaskROMParams)(implicit p: Parameters) extends LazyModule {
   val beatBytes = c.width/8
-  val node = TLManagerNode(Seq(TLManagerPortParameters(
-    Seq(TLManagerParameters(
+  val node = TLManagerNode(Seq(TLSlavePortParameters.v1(
+    Seq(TLSlaveParameters.v1(
       address            = AddressSet.misaligned(c.address, c.depth*beatBytes),
       resources          = new SimpleDevice("rom", Seq("sifive,maskrom0")).reg("mem"),
       regionType         = RegionType.UNCACHED,

src/main/scala/devices/tilelink/MasterMux.scala

@@ -8,21 +8,21 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
 
-class MasterMuxNode(uFn: Seq[TLClientPortParameters] => TLClientPortParameters)(implicit valName: ValName) extends TLCustomNode
+class MasterMuxNode(uFn: Seq[TLMasterPortParameters] => TLMasterPortParameters)(implicit valName: ValName) extends TLCustomNode
 {
   def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = {
     require (iStars == 0 && oStars == 0, "MasterMux node does not support :=* or :*=")
     require (iKnown == 2, "MasterMux node expects exactly two inputs")
     require (oKnown == 1, "MasterMux node expects exactly one output")
     (0, 0)
   }
-  def mapParamsD(n: Int, p: Seq[TLClientPortParameters]): Seq[TLClientPortParameters] = { Seq(uFn(p)) }
-  def mapParamsU(n: Int, p: Seq[TLManagerPortParameters]): Seq[TLManagerPortParameters] = { p ++ p }
+  def mapParamsD(n: Int, p: Seq[TLMasterPortParameters]): Seq[TLMasterPortParameters] = { Seq(uFn(p)) }
+  def mapParamsU(n: Int, p: Seq[TLSlavePortParameters]): Seq[TLSlavePortParameters] = { p ++ p }
 }
 
 class MuteMaster(name: String = "MuteMaster", maxProbe: Int = 0)(implicit p: Parameters) extends LazyModule
 {
-  val node = TLClientNode(Seq(TLClientPortParameters(clients = Seq(TLClientParameters(
+  val node = TLClientNode(Seq(TLMasterPortParameters.v1(clients = Seq(TLMasterParameters.v1(
     name = name,
     supportsProbe = if (maxProbe > 0) TransferSizes(1, maxProbe) else TransferSizes.none)))))
 
@@ -38,7 +38,7 @@ class MuteMaster(name: String = "MuteMaster", maxProbe: Int = 0)(implicit p: Par
   }
 }
 
-class MasterMux(uFn: Seq[TLClientPortParameters] => TLClientPortParameters)(implicit p: Parameters) extends LazyModule
+class MasterMux(uFn: Seq[TLMasterPortParameters] => TLMasterPortParameters)(implicit p: Parameters) extends LazyModule
 {
   val node = new MasterMuxNode(uFn)
 

src/main/scala/devices/tilelink/PhysicalFilter.scala

@@ -88,8 +88,8 @@ case class PhysicalFilterParams(
 
 class PhysicalFilter(params: PhysicalFilterParams)(implicit p: Parameters) extends LazyModule
 {
-  val node = TLAdapterNode(managerFn = { mp => mp.copy(
-    managers      = mp.managers.map(_.copy(alwaysGrantsT = false)),
+  val node = TLAdapterNode(managerFn = { mp => mp.v1copy(
+    managers      = mp.managers.map(_.v1copy(alwaysGrantsT = false)),
     endSinkId     = if (mp.endSinkId == 0) { 0 } else { mp.endSinkId+1 },
     minLatency    = 1 min mp.minLatency)})
 

src/main/scala/devices/tilelink/TestRAM.scala

@@ -13,8 +13,8 @@ class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int
 {
   val device = new MemoryDevice
 
-  val node = TLManagerNode(Seq(TLManagerPortParameters(
-    Seq(TLManagerParameters(
+  val node = TLManagerNode(Seq(TLSlavePortParameters.v1(
+    Seq(TLSlaveParameters.v1(
       address            = List(address),
       resources          = device.reg,
       regionType         = RegionType.UNCACHED,

src/main/scala/rocket/HellaCache.scala

@@ -177,19 +177,19 @@ abstract class HellaCache(hartid: Int)(implicit p: Parameters) extends LazyModul
     with HasNonDiplomaticTileParameters {
   protected val cfg = tileParams.dcache.get
 
-  protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLClientParameters(
+  protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1(
     name          = s"Core ${hartid} DCache",
     sourceId      = IdRange(0, 1 max cfg.nMSHRs),
     supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes))))
 
-  protected def mmioClientParameters = Seq(TLClientParameters(
+  protected def mmioClientParameters = Seq(TLMasterParameters.v1(
     name          = s"Core ${hartid} DCache MMIO",
     sourceId      = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs),
     requestFifo   = true))
 
   def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max
 
-  val node = TLClientNode(Seq(TLClientPortParameters(
+  val node = TLClientNode(Seq(TLMasterPortParameters.v1(
     cacheClientParameters ++ mmioClientParameters,
     minLatency = 1)))
 

src/main/scala/rocket/ICache.scala

@@ -51,7 +51,7 @@ class ICacheErrors(implicit p: Parameters) extends CoreBundle()(p)
 
 class ICache(val icacheParams: ICacheParams, val hartId: Int)(implicit p: Parameters) extends LazyModule {
   lazy val module = new ICacheModule(this)
-  val masterNode = TLClientNode(Seq(TLClientPortParameters(Seq(TLClientParameters(
+  val masterNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
     sourceId = IdRange(0, 1 + icacheParams.prefetch.toInt), // 0=refill, 1=hint
     name = s"Core ${hartId} ICache")))))
 
@@ -76,8 +76,8 @@ class ICache(val icacheParams: ICacheParams, val hartId: Int)(implicit p: Parame
 
   private val wordBytes = icacheParams.fetchBytes
   val slaveNode =
-    TLManagerNode(icacheParams.itimAddr.toSeq.map { itimAddr => TLManagerPortParameters(
-      Seq(TLManagerParameters(
+    TLManagerNode(icacheParams.itimAddr.toSeq.map { itimAddr => TLSlavePortParameters.v1(
+      Seq(TLSlaveParameters.v1(
         address         = Seq(AddressSet(itimAddr, size-1)),
         resources       = device.reg("mem"),
         regionType      = RegionType.IDEMPOTENT,

src/main/scala/rocket/ScratchpadSlavePort.scala

@@ -19,8 +19,8 @@ class ScratchpadSlavePort(address: Seq[AddressSet], coreDataBytes: Int, usingAto
 
   val device = new SimpleDevice("dtim", Seq("sifive,dtim0"))
 
-  val node = TLManagerNode(Seq(TLManagerPortParameters(
-    Seq(TLManagerParameters(
+  val node = TLManagerNode(Seq(TLSlavePortParameters.v1(
+    Seq(TLSlaveParameters.v1(
       address            = address,
       resources          = device.reg("mem"),
       regionType         = RegionType.IDEMPOTENT,

src/main/scala/subsystem/Ports.scala

@@ -135,8 +135,8 @@ trait CanHaveMasterTLMMIOPort { this: BaseSubsystem =>
 
   val mmioTLNode = TLManagerNode(
     mmioPortParamsOpt.map(params =>
-      TLManagerPortParameters(
-        managers = Seq(TLManagerParameters(
+      TLSlavePortParameters.v1(
+        managers = Seq(TLSlaveParameters.v1(
           address            = AddressSet.misaligned(params.base, params.size),
           resources          = device.ranges,
           executable         = params.executable,
@@ -170,8 +170,8 @@ trait CanHaveSlaveTLPort { this: BaseSubsystem =>
 
   val l2FrontendTLNode = TLClientNode(
     slavePortParamsOpt.map(params =>
-      TLClientPortParameters(
-        clients = Seq(TLClientParameters(
+      TLMasterPortParameters.v1(
+        clients = Seq(TLMasterParameters.v1(
           name     = portName.kebab,
           sourceId = IdRange(0, 1 << params.idBits))))).toSeq)
 

src/main/scala/tile/LazyRoCC.scala

@@ -236,7 +236,7 @@ class TranslatorExampleModuleImp(outer: TranslatorExample)(implicit p: Parameter
 
 class  CharacterCountExample(opcodes: OpcodeSet)(implicit p: Parameters) extends LazyRoCC(opcodes) {
   override lazy val module = new CharacterCountExampleModuleImp(this)
-  override val atlNode = TLClientNode(Seq(TLClientPortParameters(Seq(TLClientParameters("CharacterCountRoCC")))))
+  override val atlNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1("CharacterCountRoCC")))))
 }
 
 class CharacterCountExampleModuleImp(outer: CharacterCountExample)(implicit p: Parameters) extends LazyRoCCModuleImp(outer)

src/main/scala/tilelink/AddressAdjuster.scala

@@ -30,7 +30,7 @@ class AddressAdjuster(mask: BigInt, adjustableRegion: Option[AddressSet] = Some(
   // Address Adjustment requires many things about the downstream devices, captured here as helper functions:
 
   // Report whether a region of addresses fully contains a particular manager
-  def isDeviceContainedBy(region: Seq[AddressSet], m: TLManagerParameters): Boolean = {
+  def isDeviceContainedBy(region: Seq[AddressSet], m: TLSlaveParameters): Boolean = {
     val addr = masked(m.address)
     val any_in  = region.exists { f => addr.exists { a => f.overlaps(a) } }
     val any_out = region.exists { f => addr.exists { a => !f.contains(a) } }
@@ -41,7 +41,7 @@ class AddressAdjuster(mask: BigInt, adjustableRegion: Option[AddressSet] = Some(
   }
 
   // Confirm that bits of an address are repeated according to the mask
-  def requireMaskRepetition(managers: Seq[TLManagerParameters]): Unit = managers.map { m =>
+  def requireMaskRepetition(managers: Seq[TLSlaveParameters]): Unit = managers.map { m =>
     val sorted = m.address.sorted
     bits.foreach { b =>
       val flipped = m.address.map(a => AddressSet((a.base ^ b) & ~a.mask, a.mask)).sorted
@@ -50,7 +50,7 @@ class AddressAdjuster(mask: BigInt, adjustableRegion: Option[AddressSet] = Some(
   }
 
   // Confirm that everything supported by the remote PMA (which will be the final PMA) can be taken to the error device
-  def requireErrorSupport(errorDev: TLManagerParameters, managers: Seq[TLManagerParameters]): Unit = managers.map { m =>
+  def requireErrorSupport(errorDev: TLSlaveParameters, managers: Seq[TLSlaveParameters]): Unit = managers.map { m =>
     require (errorDev.supportsAcquireT  .contains(m.supportsAcquireT  ), s"Error device cannot cover ${m.name}'s AcquireT")
     require (errorDev.supportsAcquireB  .contains(m.supportsAcquireB  ), s"Error device cannot cover ${m.name}'s AcquireB")
     require (errorDev.supportsArithmetic.contains(m.supportsArithmetic), s"Error device cannot cover ${m.name}'s Arithmetic")
@@ -62,14 +62,14 @@ class AddressAdjuster(mask: BigInt, adjustableRegion: Option[AddressSet] = Some(
   }
 
   // Confirm that a subset of managers have homogeneous FIFO ids
-  def requireFifoHomogeneity(managers: Seq[TLManagerParameters]): Unit = managers.map { m =>
+  def requireFifoHomogeneity(managers: Seq[TLSlaveParameters]): Unit = managers.map { m =>
     require(m.fifoId.isDefined && m.fifoId == managers.head.fifoId,
       s"${m.name} had fifoId ${m.fifoId}, " +
       s"which was not homogeneous (${managers.map(s => (s.name, s.fifoId))}) ")
   }
 
   // Confirm that a particular manager r can successfully handle all operations targetting another manager l
-  def requireContainerSupport(l: TLManagerParameters, r: TLManagerParameters): Unit = {
+  def requireContainerSupport(l: TLSlaveParameters, r: TLSlaveParameters): Unit = {
     require (l.regionType >= r.regionType,  s"Device ${l.name} cannot be ${l.regionType} when ${r.name} is ${r.regionType}")
     require (!l.executable || r.executable, s"Device ${l.name} cannot be executable if ${r.name} is not")
     require (!l.mayDenyPut || r.mayDenyPut, s"Device ${l.name} cannot deny Put if ${r.name} does not")
@@ -87,7 +87,7 @@ class AddressAdjuster(mask: BigInt, adjustableRegion: Option[AddressSet] = Some(
   }
 
   // Utility debug printer
-  def printManagers(kind: String, managers: Seq[TLManagerParameters]): Unit = {
+  def printManagers(kind: String, managers: Seq[TLSlaveParameters]): Unit = {
     println(s"$kind:")
     println(managers.map(m => s"\t${m.name} ${m.address.head} ${m.fifoId}").mkString("\n"))
   }
@@ -105,12 +105,12 @@ class AddressAdjuster(mask: BigInt, adjustableRegion: Option[AddressSet] = Some(
 
       val adjustableRemoteManagers = remote.managers.flatMap { m =>
         val intersection = m.address.flatMap(a => adjustableRegion.map(a.intersect(_))).flatten
-        if (intersection.isEmpty) None else Some(m.copy(address = intersection))
+        if (intersection.isEmpty) None else Some(m.v1copy(address = intersection))
       }
 
       val fixedRemoteManagers = remote.managers.flatMap { m =>
         val subtraction = m.address.flatMap(a => adjustableRegion.map(a.subtract(_))).flatten
-        if (subtraction.isEmpty) None else Some(m.copy(address = subtraction))
+        if (subtraction.isEmpty) None else Some(m.v1copy(address = subtraction))
       }
 
       if (false) {
@@ -156,7 +156,7 @@ class AddressAdjuster(mask: BigInt, adjustableRegion: Option[AddressSet] = Some(
         // Any address space holes in the local adjustable region will be plugged with the error device.
         // All other PMAs are replaced with the capabilities of the remote path, since that's all we can know statically.
         // Capabilities supported by the remote but not the local will result in dynamic re-reouting to the error device.
-        l.copy(
+        l.v1copy(
           address            = AddressSet.unify(masked(l.address) ++ (if (l == errorDev) holes else Nil)),
           regionType         = r.regionType,
           executable         = r.executable,
@@ -176,24 +176,24 @@ class AddressAdjuster(mask: BigInt, adjustableRegion: Option[AddressSet] = Some(
 
       // Actually rewrite the PMAs for the adjustable remote region too, to account for the differing FIFO domains under the mask
       val newRemotes = ids.tail.zipWithIndex.flatMap { case (id, i) => adjustableRemoteManagers.map { r =>
-        r.copy(
+        r.v1copy(
           address = AddressSet.unify(masked(r.address, offset = id)),
           fifoId = Some(i+1))
       } }
 
       // Relable the FIFO domains for certain manager subsets
       val fifoIdFactory = TLXbar.relabeler()
-      def relabelFifo(managers: Seq[TLManagerParameters]): Seq[TLManagerParameters] = {
+      def relabelFifo(managers: Seq[TLSlaveParameters]): Seq[TLSlaveParameters] = {
         val fifoIdMapper = fifoIdFactory()
-        managers.map(m => m.copy(fifoId = m.fifoId.map(fifoIdMapper(_))))
+        managers.map(m => m.v1copy(fifoId = m.fifoId.map(fifoIdMapper(_))))
       }
 
       val newManagerList =
         relabelFifo(newLocals ++ newRemotes) ++
         relabelFifo(fixedLocalManagers) ++
         relabelFifo(fixedRemoteManagers)
 
-      Seq(local.copy(
+      Seq(local.v1copy(
         managers   = newManagerList,
         endSinkId  = local.endSinkId + remote.endSinkId,
         minLatency = local.minLatency min remote.minLatency))