Add full_data to pipelined-mul-unit

chipsalliance · Feb 29, 2024 · f8105ce · f8105ce
1 parent 5a17c56
commit f8105ce
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/src/main/scala/rocket/Multiplier.scala b/src/main/scala/rocket/Multiplier.scala
@@ -207,4 +207,5 @@ class PipelinedMultiplier(width: Int, latency: Int, nXpr: Int = 32, aluFn: ALUFN
   io.resp.valid := resp.valid
   io.resp.bits.tag := resp.bits.tag
   io.resp.bits.data := Pipe(in.valid, muxed, latency-1).bits
+  io.resp.bits.full_data := Pipe(in.valid, prod, latency-1).bits.asUInt
 }