Add scalar FPU-to-vector support

chipsalliance · Jan 26, 2024 · fb3c8dd · fb3c8dd
1 parent 3172ee6
commit fb3c8dd
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Showing 4 changed files with 25 additions and 19 deletions.
diff --git a/src/main/scala/rocket/VectorUnit.scala b/src/main/scala/rocket/VectorUnit.scala
@@ -74,6 +74,9 @@ class RocketVectorUnitModuleImp(outer: RocketVectorUnit) extends LazyModuleImp(o
     val core = new VectorCoreIO
     val tlb = Flipped(new DCacheTLBPort)
     val dmem = new HellaCacheIO
+
+    val fp_req = Decoupled(new FPInput())
+    val fp_resp = Flipped(Decoupled(new FPResult()))
   })
 }
 

diff --git a/src/main/scala/tile/FPU.scala b/src/main/scala/tile/FPU.scala
@@ -889,6 +889,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
   val divSqrt_wen = WireDefault(false.B)
   val divSqrt_inFlight = WireDefault(false.B)
   val divSqrt_waddr = Reg(UInt(5.W))
+  val divSqrt_cp = Reg(Bool())
   val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
   val divSqrt_wdata = Wire(UInt((fLen+1).W))
   val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
@@ -953,6 +954,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
   }
 
   val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
+  val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
   val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
   val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
   val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
@@ -970,7 +972,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
     DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
   }
 
-  when (wbInfo(0).cp && wen(0)) {
+  when (wb_cp && wen(0)) {
     io.cp_resp.bits.data := wdata
     io.cp_resp.valid := true.B
   }
@@ -1001,6 +1003,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
     val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
     when (divSqrt_inValid) {
       divSqrt_waddr := mem_reg_inst(11,7)
+      divSqrt_cp := mem_cp_valid
     }
 
     ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")

diff --git a/src/main/scala/tile/LazyRoCC.scala b/src/main/scala/tile/LazyRoCC.scala
@@ -87,7 +87,7 @@ trait HasLazyRoCC extends CanHavePTW { this: BaseTile =>
 }
 
 trait HasLazyRoCCModule extends CanHavePTWModule
-    with HasCoreParameters { this: RocketTileModuleImp with HasFpuOpt =>
+    with HasCoreParameters { this: RocketTileModuleImp =>
 
   val (respArb, cmdRouter) = if(outer.roccs.nonEmpty) {
     val respArb = Module(new RRArbiter(new RoCCResponse()(outer.p), outer.roccs.size))
@@ -100,23 +100,6 @@ trait HasLazyRoCCModule extends CanHavePTWModule
       dcachePorts += dcIF.io.cache
       respArb.io.in(i) <> Queue(rocc.module.io.resp)
     }
-
-    fpuOpt foreach { fpu =>
-      val nFPUPorts = outer.roccs.count(_.usesFPU)
-      if (usingFPU && nFPUPorts > 0) {
-        val fpArb = Module(new InOrderArbiter(new FPInput()(outer.p), new FPResult()(outer.p), nFPUPorts))
-        val fp_rocc_ios = outer.roccs.filter(_.usesFPU).map(_.module.io)
-        fpArb.io.in_req <> fp_rocc_ios.map(_.fpu_req)
-        fp_rocc_ios.zip(fpArb.io.in_resp).foreach {
-          case (rocc, arb) => rocc.fpu_resp <> arb
-        }
-        fpu.io.cp_req <> fpArb.io.out_req
-        fpArb.io.out_resp <> fpu.io.cp_resp
-      } else {
-        fpu.io.cp_req.valid := false.B
-        fpu.io.cp_resp.ready := false.B
-      }
-    }
     (Some(respArb), Some(cmdRouter))
   } else {
     (None, None)

diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
@@ -223,4 +223,21 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
 
 trait HasFpuOpt { this: RocketTileModuleImp =>
   val fpuOpt = outer.tileParams.core.fpu.map(params => Module(new FPU(params)(outer.p)))
+  fpuOpt.foreach { fpu =>
+    val nRoCCFPUPorts = outer.roccs.count(_.usesFPU)
+    val nFPUPorts = nRoCCFPUPorts + outer.rocketParams.core.useVector.toInt
+    val fpArb = Module(new InOrderArbiter(new FPInput()(outer.p), new FPResult()(outer.p), nFPUPorts))
+    fpu.io.cp_req <> fpArb.io.out_req
+    fpArb.io.out_resp <> fpu.io.cp_resp
+
+    val fp_rocc_ios = outer.roccs.filter(_.usesFPU).map(_.module.io)
+    for (i <- 0 until nRoCCFPUPorts) {
+      fpArb.io.in_req(i) <> fp_rocc_ios(i).fpu_req
+      fp_rocc_ios(i).fpu_resp <> fpArb.io.in_resp(i)
+    }
+    outer.vector_unit.foreach(vu => {
+      fpArb.io.in_req(nRoCCFPUPorts) <> vu.module.io.fp_req
+      vu.module.io.fp_resp <> fpArb.io.in_resp(nRoCCFPUPorts)
+    })
+  }
 }