Chisel compile warning: Chisel3 packages imports

[ingallsj]

Type of change: other enhancement (paying off technical debt)
Impact: no functional change
Development Phase: implementation

fix these Chisel compile warnings:

[warn] /rocket-chip/src/main/scala/util/DescribedSRAM.scala:7:34: imported `Annotated' is permanently hidden by definition of object Annotated in package util
[warn] import freechips.rocketchip.util.Annotated
[warn]                                  ^
[warn] /rocket-chip/src/main/scala/amba/ahb/Monitor.scala:17:72: type Reset in package core is deprecated (since 3.2): Use the version in chisel3._
[warn]   def legalize(bundle: AHBSlaveBundle, edge: AHBEdgeParameters, reset: Reset): Unit
[warn]                                                                        ^
[warn] /rocket-chip/src/main/scala/amba/ahb/Monitor.scala:30:73: type Reset in package core is deprecated (since 3.2): Use the version in chisel3._
[warn]   def legalize(bundle: AHBMasterBundle, edge: AHBEdgeParameters, reset: Reset): Unit
[warn]                                                                         ^
[warn] /rocket-chip/src/main/scala/devices/debug/Periphery.scala:181:73: value IntParam in package core is deprecated (since 3.2): Use the version in chisel3.experimental._
[warn] class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam(tickDelay)))
[warn]                                                                         ^
[warn] /rocket-chip/src/main/scala/diplomacy/BundleBridge.scala:63:38: value DataMirror in package core is deprecated (since 3.2): Use the version in chisel3.experimental._
[warn]     getElements(in).foreach { elt => DataMirror.directionOf(elt) match {
[warn]                                      ^
[warn] /rocket-chip/src/main/scala/diplomacy/BundleBridge.scala:64:12: value ActualDirection in package core is deprecated (since 3.2): Use the version in chisel3._
[warn]       case ActualDirection.Output => ()
[warn]            ^
[warn] /rocket-chip/src/main/scala/diplomacy/BundleBridge.scala:65:12: value ActualDirection in package core is deprecated (since 3.2): Use the version in chisel3._
[warn]       case ActualDirection.Unspecified => ()
[warn]            ^
[warn] /rocket-chip/src/main/scala/prci/ResetWrangler.scala:32:21: value withClockAndReset in package experimental is deprecated (since 3.2): Use the version in chisel3._
[warn]     val debounced = withClockAndReset(slowIn.clock, causes) {
[warn]                     ^
[warn] /rocket-chip/src/main/scala/prci/TestClockSource.scala:16:23: value DoubleParam in package core is deprecated (since 3.2): Use the version in chisel3.experimental._
[warn]   "PERIOD_PS" -> core.DoubleParam(1000000/freqMHz)
[warn]                       ^
[warn] /rocket-chip/src/main/scala/rocket/CSR.scala:393:17: value withClock in package experimental is deprecated (since 3.2): Use the version in chisel3._
[warn]   val reg_wfi = withClock(io.ungated_clock) { Reg(init=Bool(false)) }
[warn]                 ^
[warn] /rocket-chip/src/main/scala/rocket/CSR.scala:403:57: value withClock in package experimental is deprecated (since 3.2): Use the version in chisel3._
[warn]   val reg_cycle = if (enableCommitLog) reg_instret else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall) }
[warn]                                                         ^
[warn] /rocket-chip/src/main/scala/rocket/Frontend.scala:84:12: value withReset in package experimental is deprecated (since 3.2): Use the version in chisel3._
[warn]   val fq = withReset(reset || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 5, flow = true)) }
[warn]            ^
[warn] /rocket-chip/src/main/scala/rocket/Frontend.scala:96:3: value withClock in package experimental is deprecated (since 3.2): Use the version in chisel3._
[warn]   withClock (gated_clock) { // entering gated-clock domain
[warn]   ^
[warn] /rocket-chip/src/main/scala/rocket/PTW.scala:115:3: value withClock in package experimental is deprecated (since 3.2): Use the version in chisel3._
[warn]   withClock (gated_clock) { // entering gated-clock domain
[warn]   ^
[warn] /rocket-chip/src/main/scala/rocket/RocketCore.scala:927:20: value withClock in package experimental is deprecated (since 3.2): Use the version in chisel3._
[warn]   val rocketImpl = withClock (gated_clock) { new RocketImpl }
[warn]                    ^
[warn] /rocket-chip/src/main/scala/tile/FPU.scala:938:17: value withClock in package experimental is deprecated (since 3.2): Use the version in chisel3._
[warn]   val fpuImpl = withClock (gated_clock) { new FPUImpl }
[warn]                 ^
[warn] /rocket-chip/src/main/scala/tilelink/Monitor.scala:23:55: type Reset in package core is deprecated (since 3.2): Use the version in chisel3._
[warn]   def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
[warn]                                                       ^
[warn] /rocket-chip/src/main/scala/tilelink/Monitor.scala:745:55: type Reset in package core is deprecated (since 3.2): Use the version in chisel3._
[warn]   def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset) {
[warn]                                                       ^
[warn] /rocket-chip/src/main/scala/util/Annotations.scala:175:40: value dontTouch in package core is deprecated (since 3.2): Use the version in chisel3._
[warn]      case elt: Element => chisel3.core.dontTouch(elt)
[warn]                                        ^
[warn] /rocket-chip/src/main/scala/util/HeterogeneousBag.scala:9:68: type Record in package core is deprecated (since 3.2): Use the version in chisel3._
[warn] final case class HeterogeneousBag[T <: Data](elts: Seq[T]) extends Record with collection.IndexedSeq[T] {
[warn]                                                                    ^
[warn] /rocket-chip/src/main/scala/util/ResetCatchAndSync.scala:27:3: value withReset in package experimental is deprecated (since 3.2): Use the version in chisel3._
[warn]   withReset(post_psd_reset) {
[warn]   ^
[warn] /rocket-chip/src/main/scala/util/ResetCatchAndSync.scala:38:5: value withClockAndReset in package experimental is deprecated (since 3.2): Use the version in chisel3._
[warn]     withClockAndReset(clk, rst) {
[warn]     ^