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AsyncResetReg: use chisel3 resets #2397

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Apr 5, 2020
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AsyncResetReg: use chisel3 resets #2397

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4 changes: 3 additions & 1 deletion src/main/scala/util/AsyncResetReg.scala
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Expand Up @@ -2,7 +2,9 @@

package freechips.rocketchip.util

import Chisel._
import Chisel.{defaultCompileOptions => _, _}
import freechips.rocketchip.util.CompileOptions.NotStrictInferReset

import chisel3.{withClockAndReset, withReset, RawModule}

/** This black-boxes an Async Reset
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