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Hypervisor: encodeVirtualAddress extra MSB to canonicalize VS-disabled #3314

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merged 1 commit into from
Mar 21, 2023
Merged

Hypervisor: encodeVirtualAddress extra MSB to canonicalize VS-disabled #3314

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7 changes: 4 additions & 3 deletions src/main/scala/rocket/RocketCore.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -1092,9 +1092,10 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else {
// efficient means to compress 64-bit VA into vaddrBits+1 bits
// (VA is bad if VA(vaddrBits) != VA(vaddrBits-1))
val a = a0.asSInt >> vaddrBits
val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1))
Cat(msb, ea(vaddrBits-1,0))
val b = vaddrBitsExtended-1
val a = (a0 >> b).asSInt
val msb = Mux(a === 0.S || a === -1.S, ea(b), !ea(b-1))
Cat(msb, ea(b-1, 0))
}

class Scoreboard(n: Int, zero: Boolean = false)
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2 changes: 1 addition & 1 deletion src/main/scala/tile/BaseTile.scala
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Expand Up @@ -190,7 +190,7 @@ trait HasTileParameters extends HasNonDiplomaticTileParameters {
}
def vpnBits: Int = vaddrBits - pgIdxBits
def ppnBits: Int = paddrBits - pgIdxBits
def vpnBitsExtended: Int = vpnBits + (vaddrBits < xLen).toInt
def vpnBitsExtended: Int = vpnBits + (if (vaddrBits < xLen) 1 + usingHypervisor.toInt else 0)
def vaddrBitsExtended: Int = vpnBitsExtended + pgIdxBits
}

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