Merge pull request #386 from antmicro/dependabot/submodules/yosys-bf8… · chipsalliance/synlig@0b312c0

Commit

Merge pull request #386 from antmicro/dependabot/submodules/yosys-bf8…

…5dfe

Bump yosys from `84f0df1` to `bf85dfe`

kamilrakoczy committed Feb 1, 2022

2 parents ddbac4e + 659d6a5 commit 0b312c0

yosys

Submodule yosys updated 35 files

+1 −1		Makefile
+5 −0		backends/btor/btor.cc
+36 −0		backends/cxxrtl/cxxrtl.h
+17 −1		backends/cxxrtl/cxxrtl_backend.cc
+5 −1		backends/firrtl/firrtl.cc
+5 −0		backends/smt2/smt2.cc
+5 −0		backends/smv/smv.cc
+5 −1		backends/verilog/verilog_backend.cc
+51 −0		kernel/calc.cc
+40 −0		kernel/celledges.cc
+14 −15		kernel/celltypes.h
+33 −2		kernel/consteval.h
+312 −0		kernel/mem.cc
+30 −0		kernel/mem.h
+1 −1		kernel/qcsat.cc
+45 −2		kernel/rtlil.cc
+7 −0		kernel/rtlil.h
+100 −0		kernel/satgen.cc
+1 −1		manual/PRESENTATION_Prog/Makefile
+1 −1		passes/cmds/clean_zerowidth.cc
+4 −0		passes/cmds/stat.cc
+10 −18		passes/memory/memory_bram.cc
+112 −98		passes/opt/opt_dff.cc
+337 −60		passes/opt/opt_reduce.cc
+6 −0		passes/sat/sim.cc
+2 −0		passes/techmap/Makefile.inc
+76 −0		passes/techmap/bmuxmap.cc
+80 −0		passes/techmap/demuxmap.cc
+25 −1		passes/techmap/simplemap.cc
+45 −1		passes/tests/test_cell.cc
+49 −23		techlibs/common/simlib.v
+38 −1		techlibs/common/techmap.v
+2 −2		techlibs/quicklogic/synth_quicklogic.cc
+117 −0		tests/opt/opt_reduce_bmux.ys
+91 −0		tests/opt/opt_reduce_demux.ys

Please sign in to comment.