Stable rs feature branch merge (#2125)

Squash-merge of a feature branch ( https://github.com/alaindargelas/synlig/tree/stable_rs )

New features, bug fixes and tests (added in `tests/simple_tests` and the passlist).

  * Update to latest UHDM/Surelog
  * Fix parameter type bug
  * BlackBox attribute support
  * int pattern assign support
  * Rewrite rule for for_loop
  * Latch fix
  * Package enum const pushing
  * Struct and multi-dim hier path
  * process_logic_var trial
  * struct instance hier path
  * address assert
  * logic_var accepted in packed_array_var
  * packed_array_var fix
  * Support for 3 signals in sensitivity list

CMakeLists.txt

@@ -9,7 +9,7 @@ cmake_minimum_required(VERSION 3.20 FATAL_ERROR)
 # can also be installed on the system. This cmake is largely copied from the
 # Surelog cmake
 
-project(SYNLIG VERSION 1.76)
+project(SYNLIG VERSION 1.82)
 
 # Detect build type, fallback to release and throw a warning if use didn't
 # specify any

frontends/systemverilog/uhdm_ast.h

@@ -30,6 +30,11 @@ class UhdmAst
     // ChildrenNodeTypes that are present in the given object.
     void visit_one_to_one(const std::vector<int> child_node_types, vpiHandle parent_handle, const std::function<void(::Yosys::AST::AstNode *)> &f);
 
+    // Iterates through one-to-many relationships from given parent
+    // node through the VPI interface, visiting child nodes belonging to
+    // ChildrenNodeTypes that are present in the given object.
+    void iterate_one_to_many(const std::vector<int> child_node_types, vpiHandle parent_handle, const std::function<void(vpiHandle)> &f);
+
     // Visit children of type vpiRange that belong to the given parent node.
     void visit_range(vpiHandle obj_h, const std::function<void(::Yosys::AST::AstNode *)> &f);
 
@@ -177,6 +182,7 @@ class UhdmAst
     void process_type_parameter();
     void simplify_parameter(::Yosys::AST::AstNode *parameter, ::Yosys::AST::AstNode *module_node = nullptr);
     void process_unsupported_stmt(const UHDM::BaseClass *object, bool is_error = true);
+    void process_array_expr(const UHDM::BaseClass *object);
 
     UhdmAst(UhdmAst *p, UhdmAstShared &s, const std::string &i) : parent(p), shared(s), indent(i)
     {

tests/formal/passlist.txt

@@ -40,6 +40,7 @@ simple:BitSelectOfParameterPassedToSubmoduleInGenForOfSubmodule/top.sv
 simple:BitSelectPartSelectInFunction/top.sv
 simple:bitwise_operations/top.sv
 simple:bitwise_operations_reverted_range/top.sv
+simple:BlackBox/cells.sv
 simple:BreakContinueWhile/top.sv
 simple:BreakWhile/top.sv
 simple:CaseInside/top.sv
@@ -116,7 +117,9 @@ simple:ImportTypeOfPort/top.sv
 simple:IndexedPartSelect/top.sv
 simple:IndexedPartSelectInFor/top.sv
 simple:IndexedPartSelectInUniqueCase/top.sv
+simple:IndexedPartSelectNeg/dut.sv
 simple:IndexedPartSelectOfMember/top.sv
+simple:IndexedPartSelectPos/dut.sv
 simple:InterfaceAsPort/top.sv
 simple:InterfaceAsPortAssignValueInSubmodule/top.sv
 simple:InterfaceVariable/top.sv
@@ -133,6 +136,12 @@ simple:ModuleInstantiationAndIndirectParams/dut.sv
 simple:ModuleUsingStuctInput/top.sv
 simple:MonitorInputPort/top.sv
 simple:MultiAssignmentPatternOfConcat/top.sv
+simple:MultiDimHierPath/dut.sv
+simple:MultiDimHierPath2/dut.sv
+simple:MultiDimHierPath3/dut.sv
+simple:MultiDimHierPath4/dut.sv
+simple:MultiDimHierPath5/dut.sv
+simple:MultiDimHierPath6/dut.sv
 simple:MultipleAssignments/top.sv
 simple:MultipleCells/top.sv
 simple:NegationAsParameterOfInstance/top.sv
@@ -146,6 +155,8 @@ simple:NestedParamSubstitution/top.sv
 simple:NestedSelectOnInputPortInGenscope/top.sv
 simple:NestedSelectOnVarInGenscope/top.sv
 simple:NestedStructArrayParameterInitializedByPatternPassedAsPort/top.sv
+simple:NoEdge/dut.sv
+simple:NoLatch/dut.sv
 simple:OneAlwaysComb/dut.v
 simple:OneCast/dut.v
 simple:OneConcat/dut.v
@@ -157,6 +168,7 @@ simple:OneReplicate/dut.v
 simple:OneStruct/dut.sv
 simple:OneSysFunc/dut.v
 simple:PackageCast/dut.v
+simple:PackageEnumConstPush/dut.sv
 simple:PackageLogicTypespec/dut.sv
 simple:PackedArray/top.sv
 simple:PackedArrayPort/top.sv
@@ -182,6 +194,7 @@ simple:ParameterPassedToSubmoduleInGenscopeOfSubmodule/top.sv
 simple:ParameterPassedToSubmoduleOfSubmodule/top.sv
 simple:ParameterRangeUsingDot/top.sv
 simple:ParameterSizeOfInstance/top.sv
+simple:ParameterType/dut.sv
 simple:ParameterUnpackedArray/top.sv
 simple:ParameterUnpackedLogicArray/top.sv
 simple:ParameterUnsignedInt/top.sv
@@ -210,12 +223,14 @@ simple:ReturnFunctionCall/top.sv
 simple:rsp_gen_minimal/dut.v
 simple:SelectOnMemberSelectedFrom2DArray/top.sv
 simple:SelfPartSelectInBitSelect/top.sv
+simple:SelfSelectsInBitSelectAfterBitSelect/top.sv
 simple:serv-minimal/src/serv_1.1.0/rtl/serv_ctrl.v
 simple:ShiftTernary/top.sv
 simple:SignedWire/top.sv
 simple:simple_unary_op_minus/simple_unary_op_minus.sv
 simple:simple_unary_op_not_log/simple_unary_op_not_log.sv
 simple:simple_unary_op_plus/simple_unary_op_plus.sv
+simple:SimplifyHierPath/dut.sv
 simple:SizeOfGeneratedWireArray/top.sv
 simple:SizeOfUnsignedParameter/top.sv
 simple:StreamOp/dut.sv
@@ -235,9 +250,12 @@ simple:SubmoduleInGenScopeWithGenScopeParametrizedByParameterFromTopModule/top.s
 simple:SumOfParameters/top.sv
 simple:SumOfParametersInNestedForLoops/top.sv
 simple:synthesis/dff.sv
+simple:TypedefAlias/dut.v
+simple:TypedefAliasInPackage/top.sv
 simple:TypedefedFunctionArgument/top.sv
 simple:TypedefedFunctionReturn/top.sv
 simple:TypedefedRangedFunctionArgument/top.sv
+simple:TypedefEnum/top.sv
 simple:TypedefInModule/top.sv
 simple:TypedefInModulePort/top.sv
 simple:TypedefOnFileLevel/top.sv
@@ -262,13 +280,15 @@ simple:UnsizedConstant/top.sv
 simple:UnsizedConstantsParameterParsing/top.sv
 simple:UnsizedConstantsParsing/top.sv
 simple:VarInFor/top.sv
+simple:VarPassedTo2Submodules/top.sv
 simple:VarSelect/top.sv
 simple:WireNotStartingFromZero/top.sv
 simple:xor_assignment/top.sv
 sv2v:basic/clip_add.sv
 sv2v:basic/clip_mul.sv
 sv2v:basic/duplicate_genvar_shadow.sv
 sv2v:basic/empty_task.sv
+sv2v:basic/expr_attr.sv
 sv2v:basic/function_reorder_resolve.sv
 sv2v:basic/gate.sv
 sv2v:basic/genblk_implicit.sv
@@ -279,10 +299,13 @@ sv2v:basic/shift.sv
 sv2v:basic/simplify_arg_shadow.sv
 sv2v:basic/simplify_binop.sv
 sv2v:basic/simplify_genvar_shadow.sv
+sv2v:basic/simplify_localparam_shadow.sv
 sv2v:basic/simplify_scope.sv
 sv2v:basic/simplify_type.sv
 sv2v:basic/string_param_plain.sv
 sv2v:basic/typeof_op.sv
+sv2v:core/always_attr.sv
+sv2v:core/always_attr.v
 sv2v:core/always_latch.sv
 sv2v:core/always_latch.v
 sv2v:core/ambiguous_tore.v
@@ -320,6 +343,8 @@ sv2v:core/header_import.sv
 sv2v:core/header_import.v
 sv2v:core/input_int.sv
 sv2v:core/input_int.v
+sv2v:core/input_reg.sv
+sv2v:core/input_reg.v
 sv2v:core/interface_array_indirect.v
 sv2v:core/interface_array_single.v
 sv2v:core/interface_based_typedef.v
@@ -338,6 +363,7 @@ sv2v:core/logic_struct_select.v
 sv2v:core/log_op.v
 sv2v:core/multipack.v
 sv2v:core/multipack_delayed.v
+sv2v:core/multipack_inline.v
 sv2v:core/multipack_struct_cast.v
 sv2v:core/multi_array_decl.sv
 sv2v:core/multi_array_decl.v
@@ -364,6 +390,8 @@ sv2v:core/package_enum_4.sv
 sv2v:core/package_enum_4.v
 sv2v:core/package_enum_5.sv
 sv2v:core/package_enum_5.v
+sv2v:core/package_export_first.sv
+sv2v:core/package_export_first.v
 sv2v:core/package_export_nothing.sv
 sv2v:core/package_export_nothing.v
 sv2v:core/package_export_wildcard.sv
@@ -417,7 +445,6 @@ sv2v:core/struct_array_param.sv
 sv2v:core/struct_array_param.v
 sv2v:core/struct_bit_struct.sv
 sv2v:core/struct_bit_struct.v
-sv2v:core/struct_const.sv
 sv2v:core/struct_const.v
 sv2v:core/struct_hier_nocast.sv
 sv2v:core/struct_hier_nocast.v
@@ -428,10 +455,10 @@ sv2v:core/struct_part_select_param.v
 sv2v:core/struct_shadow.v
 sv2v:core/struct_tern.sv
 sv2v:core/struct_tern.v
-sv2v:core/tf_block.sv
-sv2v:core/tf_block.v
 sv2v:core/time.v
 sv2v:core/top_tf.v
+sv2v:core/typename_deep.sv
+sv2v:core/typename_deep.v
 sv2v:core/typeof_port.sv
 sv2v:core/typeof_port.v
 sv2v:core/union.v
@@ -444,6 +471,7 @@ sv2v:core/unused_imports.v
 sv2v:core/wire_reg.sv
 sv2v:core/wire_reg.v
 sv2v:define/main.v
+sv2v:dump/example.sv
 sv2v:error/case_multiple_defaults.sv
 sv2v:error/decl_const_var_uninit.sv
 sv2v:error/enum_conflict.sv
@@ -454,6 +482,7 @@ sv2v:error/macro_args_empty.sv
 sv2v:error/macro_arg_bad_name.sv
 sv2v:error/size_cast_neg_lit_1.sv
 sv2v:error/size_cast_neg_lit_2.sv
+sv2v:error/typeof_atom_bit.sv
 sv2v:lex/block_comment.sv
 sv2v:lex/block_comment.v
 sv2v:lex/comment_no_space.sv
@@ -470,6 +499,7 @@ sv2v:lex/number_literal_whitespace.v
 sv2v:lex/string_macro.v
 sv2v:lex/undefineall.sv
 sv2v:lex/undefineall.v
+sv2v:lex/utf8.sv
 sv2v:lib/empty.v
 sv2v:nosim/min_typ_max.sv
 sv2v:relong/alu.sv
@@ -501,11 +531,15 @@ sv2v:relong/split_struct.v
 sv2v:relong/struct.v
 sv2v:relong/typedef.sv
 sv2v:relong/typedef.v
+sv2v:search/apple.sv
+sv2v:search/misdirect.sv
+sv2v:warning/class.sv
+sv2v:warning/function.sv
 sv2v:warning/interface.sv
 sv2v:warning/localparam.sv
 sv2v:warning/package.sv
+sv2v:warning/task.sv
 sv2v:write/one.sv
-sv2v:write/two.sv
 yosys:arch/common/add_sub.v
 yosys:arch/common/blockrom.v
 yosys:arch/common/counter.v
@@ -600,14 +634,19 @@ yosys:hana/test_parser.v
 yosys:hana/test_simulation_and.v
 yosys:hana/test_simulation_decoder.v
 yosys:liberty/small.v
+yosys:memlib/memlib_clock_sdp.v
 yosys:memlib/memlib_lut.v
 yosys:memlib/memlib_multilut.v
+yosys:memlib/memlib_wide_read.v
 yosys:memlib/memlib_wide_sdp.v
 yosys:memlib/memlib_wide_sp.v
+yosys:memlib/memlib_wide_write.v
 yosys:memories/firrtl_938.v
 yosys:memories/implicit_en.v
+yosys:memories/issue00710.v
 yosys:memories/no_implicit_en.v
 yosys:memories/read_arst.v
+yosys:memories/read_two_mux.v
 yosys:memories/shared_ports.v
 yosys:memories/trans_addr_enable.v
 yosys:memories/trans_sdp.v
@@ -669,6 +708,7 @@ yosys:simple/const_branch_finish.v
 yosys:simple/const_fold_func.v
 yosys:simple/defvalue.sv
 yosys:simple/dff_different_styles.v
+yosys:simple/dynslice.v
 yosys:simple/forgen01.v
 yosys:simple/forgen02.v
 yosys:simple/forloops.v
@@ -695,6 +735,7 @@ yosys:simple/matching_end_labels.sv
 yosys:simple/mem2reg_bounds_tern.v
 yosys:simple/memwr_port_connection.sv
 yosys:simple/mem_arst.v
+yosys:simple/module_scope.v
 yosys:simple/module_scope_case.v
 yosys:simple/multiplier.v
 yosys:simple/named_genblk.v
@@ -733,15 +774,20 @@ yosys:various/attrib07_func_call.v
 yosys:various/constmsk_test.v
 yosys:various/const_func_block_var.v
 yosys:various/countbits.sv
+yosys:various/dynamic_part_select/forloop_select.v
 yosys:various/dynamic_part_select/forloop_select_gate.v
 yosys:various/dynamic_part_select/latch_002.v
 yosys:various/dynamic_part_select/latch_002_gate.v
 yosys:various/dynamic_part_select/latch_002_gate_good.v
 yosys:various/dynamic_part_select/latch_1990.v
 yosys:various/dynamic_part_select/latch_1990_gate.v
+yosys:various/dynamic_part_select/multiple_blocking.v
 yosys:various/dynamic_part_select/multiple_blocking_gate.v
+yosys:various/dynamic_part_select/nonblocking.v
 yosys:various/dynamic_part_select/nonblocking_gate.v
+yosys:various/dynamic_part_select/original.v
 yosys:various/dynamic_part_select/original_gate.v
+yosys:various/dynamic_part_select/reset_test.v
 yosys:various/dynamic_part_select/reset_test_gate.v
 yosys:various/dynamic_part_select/reversed_gate.v
 yosys:various/elab_sys_tasks.sv

tests/simple_tests/BlackBox/Makefile.in

@@ -0,0 +1,2 @@
+TEST_FILES := $(TEST_DIR)/cells.sv $(TEST_DIR)/dut.sv
+TOP_MODULE := dut

tests/simple_tests/BlackBox/cells.sv

@@ -0,0 +1,13 @@
+`celldefine
+(* blackbox *)
+module I_BUF #(
+  parameter WEAK_KEEPER = "NONE",
+  parameter DRIVE = "STRONG"
+  ) (
+  input logic I,
+  input logic EN,
+  output logic O
+);
+
+endmodule
+`endcelldefine

tests/simple_tests/BlackBox/dut.sv

@@ -0,0 +1,9 @@
+module dut(input logic clk, input logic I,
+input logic EN,
+output logic O1, O2);
+
+I_BUF ibuf1(I, EN, O1);
+
+I_BUF #(.WEAK_KEEPER("PULLUP")) ibuf2 (I, EN, O2);
+
+endmodule

tests/simple_tests/BlackBox/yosys_script.tcl

@@ -0,0 +1,8 @@
+source ../yosys_common.tcl
+
+prep -top \\dut
+write_verilog
+write_verilog yosys.sv
+# The sim command does not work for designs with blackbox,
+# it does not allow to add the blackboxes actual models back into the simulation 
+# sim -clock clk -rstlen 10 -vcd dump.vcd

tests/simple_tests/HighConnPackedArrayVar/Makefile.in

@@ -0,0 +1,2 @@
+TEST_FILES := $(TEST_DIR)/dut.sv
+TOP_MODULE := dut

tests/simple_tests/HighConnPackedArrayVar/dut.sv

@@ -0,0 +1,24 @@
+package prim_pad_wrapper_pkg;
+  typedef enum logic [2:0] {
+    BidirStd = 3'h0
+  } pad_type_e;
+  typedef logic [7:0] pad_pok_t;
+endpackage : prim_pad_wrapper_pkg
+
+module prim_pad_wrapper
+  import prim_pad_wrapper_pkg::*; (input pad_pok_t pok_i, output pad_pok_t pok_o);
+  assign pok_o = pok_i;
+endmodule : prim_pad_wrapper
+
+module dut
+  import prim_pad_wrapper_pkg::*; 
+  #(parameter logic [0:0][1:0] DioPadBank = '0) 
+  (input logic clk,
+   input pad_pok_t [3:0] pad_pok_i, 
+   output pad_pok_t [3:0] pad_pok_o);
+
+  prim_pad_wrapper u_dio_pad (
+    .pok_i      ( pad_pok_i[DioPadBank[0]]   ),
+    .pok_o      ( pad_pok_o[DioPadBank[0]]   )
+  );
+endmodule : dut

tests/simple_tests/HighConnPackedArrayVar/yosys_script.tcl

@@ -0,0 +1,6 @@
+source ../yosys_common.tcl
+
+prep -top \\dut
+write_verilog
+write_verilog yosys.sv
+sim -clock clk -rstlen 10 -vcd dump.vcd

tests/simple_tests/IndexedPartSelectNeg/Makefile.in

@@ -0,0 +1,2 @@
+TEST_FILES := $(TEST_DIR)/dut.sv
+TOP_MODULE := dut

tests/simple_tests/IndexedPartSelectNeg/dut.sv

@@ -0,0 +1,17 @@
+
+`default_nettype none
+module dut #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW)
+   (input wire             clk,
+    input wire [CTRLW-1:0] ctrl,
+    input wire [DINW-1:0]  din,
+    input wire [SELW-1:0]  sel,
+    output reg [WIDTH-1:0] dout);
+
+   localparam SLICE = WIDTH/(SELW**2);
+   always @(posedge clk) begin
+      dout <= dout + 1;
+      dout[ctrl*sel+:SLICE] <= din ;
+   end
+
+endmodule
+

tests/simple_tests/IndexedPartSelectNeg/yosys_script.tcl

@@ -0,0 +1,6 @@
+source ../yosys_common.tcl
+
+prep -top \\dut
+write_verilog
+write_verilog yosys.sv
+sim -clock clk -rstlen 10 -vcd dump.vcd

tests/simple_tests/IndexedPartSelectPos/Makefile.in

@@ -0,0 +1,2 @@
+TEST_FILES := $(TEST_DIR)/dut.sv
+TOP_MODULE := dut