Merge pull request #289 from antmicro/bump-surelog

Bump Surelog
chipsalliance · Jan 4, 2022 · 9759a66 · 9759a66
2 parents fb6df20 + 9935742
commit 9759a66
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Showing 3 changed files with 8 additions and 4 deletions.
diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
@@ -22,7 +22,10 @@ jobs:
     - name: Install dependencies
       run: |
         apt-get update -qq
-        apt install -y g++-9 build-essential cmake tclsh ant default-jre swig google-perftools libgoogle-perftools-dev python3 python3-dev uuid uuid-dev tcl-dev flex libfl-dev git pkg-config libreadline-dev bison libffi-dev wget ccache
+        apt install -y g++-9 build-essential cmake tclsh ant default-jre swig google-perftools libgoogle-perftools-dev python3 python3-dev python3-pip uuid uuid-dev tcl-dev flex libfl-dev git pkg-config libreadline-dev bison libffi-dev wget ccache
+        update-alternatives --install /usr/bin/python python /usr/bin/python3 1
+        update-alternatives --install /usr/bin/pip pip /usr/bin/pip3 1
+        pip install orderedmultidict
 
     - uses: actions/checkout@v2
       with:

diff --git a/Surelog b/Surelog
diff --git a/uhdm-tests/swerv/0001-swerv.patch b/uhdm-tests/swerv/0001-swerv.patch
@@ -87,7 +87,7 @@ index 5110c1b..8ef38e8 100644
                           ({32{w2v[j]}} & wd2[31:0]);
       end
 diff --git a/design/dec/dec_tlu_ctl.sv b/design/dec/dec_tlu_ctl.sv
-index 52a4393..b5cc73f 100644
+index 52a4393..2564a61 100644
 --- a/design/dec/dec_tlu_ctl.sv
 +++ b/design/dec/dec_tlu_ctl.sv
 @@ -191,8 +191,10 @@ module dec_tlu_ctl
@@ -156,7 +156,8 @@ index 52a4393..b5cc73f 100644
 -                                                     }));
 +                                              .dout({dec_tlu_br0_wb_pkt[6:2], dec_tlu_br1_wb_pkt[6:2]}));
 
-    rvdff #(2*$bits(dec_tlu_br0_addr_e4[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO]))
+-   rvdff #(2*$bits(dec_tlu_br0_addr_e4[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO]))
++   rvdff #(2*$bits(dec_tlu_br0_addr_e4))
          bp_wb_index_ff (.*,  .clk(e4e5_clk),
                              .din({dec_tlu_br0_addr_e4[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO],
                                    dec_tlu_br1_addr_e4[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO]}),