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applying clang-format
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@karimtera
karimtera committed Jul 21, 2022
1 parent 42db6ab commit ebd1e49
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Showing 3 changed files with 97 additions and 88 deletions.
78 changes: 42 additions & 36 deletions verilog/analysis/flow_tree.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -12,51 +12,54 @@
// See the License for the specific language governing permissions and
// limitations under the License.

#include <vector>
#include "verilog/analysis/flow_tree.h"

#include <map>
#include <string>
#include <vector>

#include "absl/status/status.h"
#include "absl/strings/str_cat.h"
#include "absl/strings/string_view.h"
#include "common/lexer/token_stream_adapter.h"
#include "verilog/parser/verilog_token_enum.h"
#include "verilog/analysis/flow_tree.h"

namespace verilog {

absl::Status FlowTree::GenerateControlFlowTree(){
int idx=0;
int current_enum=0;
for(auto u:source_sequence_){
current_enum=u.token_enum();
absl::Status FlowTree::GenerateControlFlowTree() {
int idx = 0;
int current_enum = 0;
for (auto u : source_sequence_) {
current_enum = u.token_enum();

if(current_enum == PP_ifdef || current_enum == PP_ifndef){
if (current_enum == PP_ifdef || current_enum == PP_ifndef) {
ifs_.push_back(idx);
elses_[ifs_.back()].push_back(idx);

}else if(current_enum == PP_else || current_enum == PP_elsif || current_enum == PP_endif){
} else if (current_enum == PP_else || current_enum == PP_elsif ||
current_enum == PP_endif) {
elses_[ifs_.back()].push_back(idx);
if(current_enum == PP_endif){
auto & myelses= elses_[ifs_.back()];
for(int i=0;i<myelses.size();i++){
for(int j=i+1;j<myelses.size();j++){
if(!i&&j==myelses.size()-1) continue;
edges_[myelses[i]].push_back(myelses[j]+1);
if (current_enum == PP_endif) {
auto& myelses = elses_[ifs_.back()];
for (int i = 0; i < myelses.size(); i++) {
for (int j = i + 1; j < myelses.size(); j++) {
if (!i && j == myelses.size() - 1) continue;
edges_[myelses[i]].push_back(myelses[j] + 1);
}
}
ifs_.pop_back();
}
}
idx++;
}
idx=0;
int prv_enum=0;
for(auto u:source_sequence_){
current_enum=u.token_enum();
if(current_enum != PP_else && current_enum != PP_elsif){
if(idx>0) edges_[idx-1].push_back(idx);
}else{
if(idx>0) edges_[idx-1].push_back(edges_[idx].back());
idx = 0;
int prv_enum = 0;
for (auto u : source_sequence_) {
current_enum = u.token_enum();
if (current_enum != PP_else && current_enum != PP_elsif) {
if (idx > 0) edges_[idx - 1].push_back(idx);
} else {
if (idx > 0) edges_[idx - 1].push_back(edges_[idx].back());
}
prv_enum = current_enum;
idx++;
Expand All @@ -65,22 +68,25 @@ absl::Status FlowTree::GenerateControlFlowTree(){
return absl::OkStatus();
}

absl::Status FlowTree::DepthFirstSearch(int index){
const auto & curr=source_sequence_[index];
if(curr.token_enum()!=PP_Identifier && curr.token_enum() != PP_ifndef && curr.token_enum()!=PP_ifdef
&& curr.token_enum()!=PP_define && curr.token_enum()!=PP_define_body
&& curr.token_enum()!=PP_elsif && curr.token_enum()!=PP_else && curr.token_enum()!=PP_endif) current_sequence_.push_back(curr);
for(auto u:edges_[index]){
auto status = FlowTree::DepthFirstSearch(u); // handle errors
absl::Status FlowTree::DepthFirstSearch(int index) {
const auto& curr = source_sequence_[index];
if (curr.token_enum() != PP_Identifier && curr.token_enum() != PP_ifndef &&
curr.token_enum() != PP_ifdef && curr.token_enum() != PP_define &&
curr.token_enum() != PP_define_body && curr.token_enum() != PP_elsif &&
curr.token_enum() != PP_else && curr.token_enum() != PP_endif)
current_sequence_.push_back(curr);
for (auto u : edges_[index]) {
auto status = FlowTree::DepthFirstSearch(u); // handle errors
}
if(index==source_sequence_.size()-1){
if (index == source_sequence_.size() - 1) {
variants_.push_back(current_sequence_);
}
if(curr.token_enum()!=PP_Identifier && curr.token_enum() != PP_ifndef && curr.token_enum()!=PP_ifdef
&& curr.token_enum()!=PP_define && curr.token_enum()!=PP_define_body
&& curr.token_enum()!=PP_elsif && curr.token_enum()!=PP_else && curr.token_enum()!=PP_endif) current_sequence_.pop_back();
if (curr.token_enum() != PP_Identifier && curr.token_enum() != PP_ifndef &&
curr.token_enum() != PP_ifdef && curr.token_enum() != PP_define &&
curr.token_enum() != PP_define_body && curr.token_enum() != PP_elsif &&
curr.token_enum() != PP_else && curr.token_enum() != PP_endif)
current_sequence_.pop_back();
return absl::OkStatus();
}

} // namespace verilog

} // namespace verilog
16 changes: 9 additions & 7 deletions verilog/analysis/flow_tree.h
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Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,10 @@
#ifndef VERIBLE_VERILOG_FLOW_TREE_H_
#define VERIBLE_VERILOG_FLOW_TREE_H_


#include <vector>
#include <map>
#include <string>
#include <vector>

#include "absl/status/status.h"
#include "common/lexer/token_stream_adapter.h"
#include "verilog/parser/verilog_token_enum.h"
Expand All @@ -27,19 +27,21 @@ namespace verilog {

class FlowTree {
public:
explicit FlowTree(verible::TokenSequence source_sequence): source_sequence_(std::move(source_sequence)){};
explicit FlowTree(verible::TokenSequence source_sequence)
: source_sequence_(std::move(source_sequence)){};

absl::Status GenerateControlFlowTree();
absl::Status DepthFirstSearch(int index);
std::vector<verible::TokenSequence> variants_;

private:
std::vector<int> ifs_;
std::map<int,std::vector<int>> elses_;
std::map<int,std::vector<int>> edges_;
std::map<int, std::vector<int>> elses_;
std::map<int, std::vector<int>> edges_;
verible::TokenSequence source_sequence_;
verible::TokenSequence current_sequence_;
};

} // namespace verilog
} // namespace verilog

#endif // VERIBLE_VERILOG_FLOW_TREE_H_
#endif // VERIBLE_VERILOG_FLOW_TREE_H_
91 changes: 46 additions & 45 deletions verilog/tools/preprocessor/verilog_preprocessor.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -20,16 +20,16 @@
#include "absl/status/status.h"
#include "absl/strings/str_cat.h"
#include "absl/strings/string_view.h"
#include "common/lexer/token_stream_adapter.h"
#include "common/util/file_util.h"
#include "common/util/init_command_line.h"
#include "common/util/subcommand.h"
#include "verilog/transform/strip_comments.h"
#include "verilog/parser/verilog_lexer.h"
#include "verilog/preprocessor/verilog_preprocess.h"
#include "common/lexer/token_stream_adapter.h"
#include "verilog/analysis/flow_tree.h"
#include "verilog/analysis/verilog_analyzer.h"
#include "verilog/parser/verilog_lexer.h"
#include "verilog/parser/verilog_token_enum.h"
#include "verilog/analysis/flow_tree.h"
#include "verilog/preprocessor/verilog_preprocess.h"
#include "verilog/transform/strip_comments.h"

using verible::SubcommandArgsRange;
using verible::SubcommandEntry;
Expand All @@ -55,67 +55,68 @@ static absl::Status StripComments(const SubcommandArgsRange& args,
return absl::OkStatus();
}


static absl::Status MultipleCU(const SubcommandArgsRange& args,
std::istream&, std::ostream& outs,
std::ostream&) {
static absl::Status MultipleCU(const SubcommandArgsRange& args, std::istream&,
std::ostream& outs, std::ostream&) {
if (args.empty()) {
return absl::InvalidArgumentError(
"Missing file argument.");
return absl::InvalidArgumentError("Missing file argument.");
}

for(auto source_file:args){
for (auto source_file : args) {
std::string source_contents;
if (auto status = verible::file::GetContents(source_file, &source_contents);
!status.ok()) {
return status;
}
verilog::VerilogPreprocess::Config config;
config.filter_branches=1;
//config.expand_macros=1;
config.filter_branches = 1;
// config.expand_macros=1;
verilog::VerilogPreprocess preprocessor(config);
verilog::VerilogLexer lexer(source_contents);
verible::TokenSequence lexed_sequence;
for (lexer.DoNextToken(); !lexer.GetLastToken().isEOF();
lexer.DoNextToken()) {
// For now we will store the syntax tree tokens only, ignoring all the white-space characters.
// however that should be stored to output the source code just like it was, but with conditionals filtered.
if(verilog::VerilogLexer::KeepSyntaxTreeTokens(lexer.GetLastToken())) lexed_sequence.push_back(lexer.GetLastToken());
for (lexer.DoNextToken(); !lexer.GetLastToken().isEOF();
lexer.DoNextToken()) {
// For now we will store the syntax tree tokens only, ignoring all the
// white-space characters. however that should be stored to output the
// source code just like it was, but with conditionals filtered.
if (verilog::VerilogLexer::KeepSyntaxTreeTokens(lexer.GetLastToken()))
lexed_sequence.push_back(lexer.GetLastToken());
}
verible::TokenStreamView lexed_streamview;
// Initializing the lexed token stream view.
InitTokenStreamView(lexed_sequence, &lexed_streamview);
verilog::VerilogPreprocessData preprocessed_data = preprocessor.ScanStream(lexed_streamview);
verilog::VerilogPreprocessData preprocessed_data =
preprocessor.ScanStream(lexed_streamview);
auto& preprocessed_stream = preprocessed_data.preprocessed_token_stream;
for(auto u:preprocessed_stream) outs<<*u<<'\n'; // output the preprocessed tokens.
for(auto& u:preprocessed_data.errors) outs<<u.error_message<<'\n'; // for debugging.
for (auto u : preprocessed_stream)
outs << *u << '\n'; // output the preprocessed tokens.
for (auto& u : preprocessed_data.errors)
outs << u.error_message << '\n'; // for debugging.
// parsing just as a trial
std::string post_preproc;
for(auto u:preprocessed_stream) post_preproc+=std::string{u->text()};
for (auto u : preprocessed_stream) post_preproc += std::string{u->text()};
std::string source_view{post_preproc};
verilog::VerilogAnalyzer analyzer(source_view,"file1",config);
verilog::VerilogAnalyzer analyzer(source_view, "file1", config);
auto analyze_status = analyzer.Analyze();
const auto& mydata = analyzer.Data().Contents();
/* outs<<mydata; */


/* TODO(karimtera): regarding conditionals
1) Modify VerilogPreprocess config to have a configuration to generate SV source codes for all possible variants.
2) Then use parser, directly from VerilogAnalyzer or from VerilogParser to have less dependences.
3) Now, we should have multiple trees, we need to merge them as described by Tom in Verible's issue.
4) Finally, travese the tree and output the chosen path based on definitions.
1) Modify VerilogPreprocess config to have a configuration to generate SV
source codes for all possible variants. 2) Then use parser, directly from
VerilogAnalyzer or from VerilogParser to have less dependences. 3) Now, we
should have multiple trees, we need to merge them as described by Tom in
Verible's issue. 4) Finally, travese the tree and output the chosen path
based on definitions.
*/
}
return absl::OkStatus();
}


static absl::Status GenerateVariants(const SubcommandArgsRange& args,
std::istream&, std::ostream& outs,
std::ostream&) {
std::istream&, std::ostream& outs,
std::ostream&) {
if (args.empty()) {
return absl::InvalidArgumentError(
"Missing file argument.");
return absl::InvalidArgumentError("Missing file argument.");
}

const char* source_file = args[0];
Expand All @@ -126,23 +127,23 @@ static absl::Status GenerateVariants(const SubcommandArgsRange& args,
}
verilog::VerilogLexer lexer(source_contents);
verible::TokenSequence lexed_sequence;
for (lexer.DoNextToken(); !lexer.GetLastToken().isEOF();
lexer.DoNextToken()) {
// For now we will store the syntax tree tokens only, ignoring all the white-space characters.
// however that should be stored to output the source code just like it was.
if(verilog::VerilogLexer::KeepSyntaxTreeTokens(lexer.GetLastToken())) lexed_sequence.push_back(lexer.GetLastToken());
for (lexer.DoNextToken(); !lexer.GetLastToken().isEOF();
lexer.DoNextToken()) {
// For now we will store the syntax tree tokens only, ignoring all the
// white-space characters. however that should be stored to output the
// source code just like it was.
if (verilog::VerilogLexer::KeepSyntaxTreeTokens(lexer.GetLastToken()))
lexed_sequence.push_back(lexer.GetLastToken());
}

verilog::FlowTree control_flow_tree(lexed_sequence);
auto status = control_flow_tree.GenerateControlFlowTree();
status = control_flow_tree.DepthFirstSearch(0);
int cnt=1;
for(const auto& u:control_flow_tree.variants_){
outs<<"Variant number "<<cnt++<<":\n";
for(auto k:u) outs<<k<<'\n';
int cnt = 1;
for (const auto& u : control_flow_tree.variants_) {
outs << "Variant number " << cnt++ << ":\n";
for (auto k : u) outs << k << '\n';
puts("");


}

return absl::OkStatus();
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