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Forbid implicit begin/end #1321

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suzizecat opened this issue Apr 26, 2022 · 1 comment
Open

Forbid implicit begin/end #1321

suzizecat opened this issue Apr 26, 2022 · 1 comment
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enhancement New feature or request style-linter Verilog style-linter issues

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@suzizecat
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Summary

It would be nice to have a style rule checking the presence of a pair of begin/end keywords for each construction that support it.
the obvious example would be with if/else if/else.

It might be interesting to split the case structure from the if one, as it might be convenient and less error-prone to have one-line case statements.

The name could be something like explicit-begin ou forbid-implicit-begin (a bit too long to my taste)

Test cases and examples

// This example should be diagnosed.
if my_condition // <-- issue
    signal <= 1;
else // <-- issue
    signal <= 0;

other_signal <= 1;
// This variant should NOT be diagnosed (negative test case)
// Considered correct: 
if my_condition begin
    signal <= 1;
end else begin
    signal <= 0;
end

other_signal <= 1;

This should be done regardless of the actual position of begin/end:

// This variant should NOT be diagnosed (negative test case)
// Considered correct: 
if my_condition 
begin
    signal <= 1;
end 
else 
begin
    signal <= 0;
end

other_signal <= 1;

The case situation might be a little bit trickier:

// Maybe valid ? Configuration would be nice...
case (stuff)
    0 : foo = 1; // <-- Arguably OK
    1 : foo = 0; // <-- Same
    3 :          // <-- Arguably not OK
          foo = bar;
    default:
        begin // <-- Always OK
              foo = 0;
       end
endcase

Proposal

N/A

Additional context

N/A

Best regards,
Julien FAUCHER

@suzizecat suzizecat added enhancement New feature or request style-linter Verilog style-linter issues labels Apr 26, 2022
suzizecat pushed a commit to suzizecat/verible that referenced this issue May 16, 2022
Add rule to check if the begin keyword always follows a if/else/for.
Related to chipsalliance#1321
@sconwayaus
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Also mentioned here: #2040

sconwayaus pushed a commit to sconwayaus/verible that referenced this issue Apr 25, 2024
Add rule to check if the begin keyword always follows a if/else/for.
Related to chipsalliance#1321
sconwayaus pushed a commit to sconwayaus/verible that referenced this issue Apr 25, 2024
Add rule to check if the begin keyword always follows a if/else/for.
Related to chipsalliance#1321
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Labels
enhancement New feature or request style-linter Verilog style-linter issues
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