Clock propagation enhancement #54
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I haven't actually looked at this pull request, but do please make sure we have a bunch of documentation around this. |
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Also, if there is a conflict, which one wins? |
| file << "create_clock -period " << Clock::Period(clock_wire); | ||
| file << " -waveform {" << Clock::RisingEdge(clock_wire) << " " | ||
| << Clock::FallingEdge(clock_wire) << "}"; | ||
| file << " " << Clock::WireName(clock_wire); |
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Can you explain why this is called SourcePinName, rather than SourceWireName? Does Yosys have a first class cell pin object?
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SOURCE_PIN was the attribute in Vivado, but we do use wires instead of pins.
Hence, I changed the attribute and method name according to what it really is.
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Can yosys return the wire attached to a cell pin? If so, it might make more sense to stick with SOURCE_PIN, and change this code to get the wire from the source pin?
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Conflicts? |
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
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…es/sv2v-dd95174 Bump sv2v from `9bc946c` to `dd95174`
This PR aims at solving issue #53.
Added a distinction between three types of clocks:
create_clockcommand